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gpu: nvgpu: Remove uses of platform->can_elpg
Remove newly introduced uses of gk20a_platform->can_elpg. Rename the field to can_elpg_init and replace all uses with gk20a->can_elpg. Change-Id: Id6e84d4c16159b5da80c583a8a94a9c5cc2423ec Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1480955 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -106,7 +106,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
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g->mscg_enabled =
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nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false;
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g->can_elpg =
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nvgpu_platform_is_silicon(g) ? platform->can_elpg : false;
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nvgpu_platform_is_silicon(g) ? platform->can_elpg_init : false;
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g->default_pri_timeout = platform->default_pri_timeout;
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g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
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g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
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@@ -66,7 +66,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = false,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_elpg = true,
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.enable_elcg = false,
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.enable_slcg = true,
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@@ -100,7 +100,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = false,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_elpg = true,
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.enable_elcg = false,
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.enable_slcg = true,
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@@ -134,7 +134,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = false,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_elpg = true,
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.enable_elcg = false,
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.enable_slcg = true,
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@@ -168,7 +168,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = false,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_elpg = true,
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.enable_elcg = false,
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.enable_slcg = true,
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@@ -1206,7 +1206,6 @@ static inline void get_exception_mmu_fault_info(
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void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
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{
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struct fifo_gk20a *f = NULL;
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struct gk20a_platform *platform;
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u32 engine_enum = ENGINE_INVAL_GK20A;
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u32 inst_id = 0;
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struct fifo_engine_info_gk20a *engine_info;
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@@ -1217,7 +1216,6 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
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return;
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f = &g->fifo;
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platform = dev_get_drvdata(g->dev);
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engine_info = gk20a_fifo_get_engine_info(g, engine_id);
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@@ -1230,7 +1228,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
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nvgpu_err(g, "unsupported engine_id %d", engine_id);
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if (engine_enum == ENGINE_GR_GK20A) {
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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gk20a_pmu_disable_elpg(g);
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/* resetting engine will alter read/write index.
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* need to flush circular buffer before re-enabling FECS.
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@@ -1243,7 +1241,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
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/* resetting engine using mc_enable_r() is not
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enough, we do full init sequence */
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gk20a_gr_reset(g);
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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gk20a_pmu_enable_elpg(g);
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}
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if ((engine_enum == ENGINE_GRCE_GK20A) ||
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@@ -1468,7 +1466,6 @@ static bool gk20a_fifo_handle_mmu_fault(
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bool id_is_tsg)
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{
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bool fake_fault;
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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unsigned long fault_id;
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unsigned long engine_mmu_fault_id;
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bool verbose = true;
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@@ -1479,7 +1476,7 @@ static bool gk20a_fifo_handle_mmu_fault(
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g->fifo.deferred_reset_pending = false;
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/* Disable power management */
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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gk20a_pmu_disable_elpg(g);
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if (g->ops.clock_gating.slcg_gr_load_gating_prod)
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g->ops.clock_gating.slcg_gr_load_gating_prod(g,
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@@ -1678,7 +1675,7 @@ static bool gk20a_fifo_handle_mmu_fault(
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gr_gpfifo_ctl_semaphore_access_enabled_f());
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/* It is safe to enable ELPG again. */
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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gk20a_pmu_enable_elpg(g);
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return verbose;
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@@ -3126,7 +3126,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
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struct nvgpu_alloc_obj_ctx_args *args)
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{
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struct gk20a *g = c->g;
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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struct fifo_gk20a *f = &g->fifo;
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struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
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struct tsg_gk20a *tsg = NULL;
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@@ -3281,7 +3280,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
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args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO;
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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gk20a_pmu_enable_elpg(g);
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}
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@@ -42,7 +42,7 @@ struct gk20a_platform {
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bool can_railgate_init;
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/* Should be populated at probe. */
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bool can_elpg;
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bool can_elpg_init;
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/* Should be populated at probe. */
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bool has_syncpoints;
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@@ -53,7 +53,7 @@ struct gk20a_platform vgpu_tegra_platform = {
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/* power management configuration */
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.can_railgate_init = false,
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.can_elpg = false,
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.can_elpg_init = false,
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.enable_slcg = false,
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.enable_blcg = false,
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.enable_elcg = false,
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@@ -4936,7 +4936,6 @@ clean_up:
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int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
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{
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u32 status = 0;
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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if (enable_pg == true) {
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if (g->ops.pmu.pmu_pg_engines_feature_list &&
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@@ -4946,7 +4945,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
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if (g->ops.pmu.pmu_lpwr_enable_pg)
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status = g->ops.pmu.pmu_lpwr_enable_pg(g,
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true);
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} else if (g->support_pmu && platform->can_elpg)
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} else if (g->support_pmu && g->can_elpg)
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status = gk20a_pmu_enable_elpg(g);
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} else if (enable_pg == false) {
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if (g->ops.pmu.pmu_pg_engines_feature_list &&
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@@ -4956,7 +4955,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
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if (g->ops.pmu.pmu_lpwr_disable_pg)
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status = g->ops.pmu.pmu_lpwr_disable_pg(g,
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true);
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} else if (g->support_pmu && platform->can_elpg)
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} else if (g->support_pmu && g->can_elpg)
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status = gk20a_pmu_disable_elpg(g);
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}
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@@ -337,7 +337,6 @@ u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
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int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
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{
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struct pmu_gk20a *pmu = &g->pmu;
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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u32 status = 0;
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u32 is_mscg_supported = 0;
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u32 is_rppg_supported = 0;
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@@ -364,7 +363,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
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is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g,
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present_pstate);
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if (is_rppg_supported) {
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if (g->support_pmu && platform->can_elpg)
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if (g->support_pmu && g->can_elpg)
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status = gk20a_pmu_enable_elpg(g);
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}
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@@ -1053,7 +1053,7 @@ struct gk20a_platform gk20a_tegra_platform = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = true,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_slcg = true,
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.enable_blcg = true,
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.enable_elcg = true,
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@@ -1110,7 +1110,7 @@ struct gk20a_platform gm20b_tegra_platform = {
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/* power management configuration */
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.railgate_delay_init = 500,
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.can_railgate_init = true,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_slcg = true,
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.enable_blcg = true,
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.enable_elcg = true,
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@@ -387,7 +387,7 @@ struct gk20a_platform gp10b_tegra_platform = {
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/* power management configuration */
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.can_railgate_init = true,
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.enable_elpg = true,
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.can_elpg = true,
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.can_elpg_init = true,
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.enable_blcg = true,
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.enable_slcg = true,
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.enable_elcg = true,
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