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gpu: nvgpu: resolve MISRA 10.3 violations

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MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.

This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.

JIRA NVGPU-647

Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-08-23 14:45:19 -04:00
committed by mobile promotions
parent 74639b4442
commit 2d0149c9ab
11 changed files with 101 additions and 101 deletions
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12
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -1124,20 +1124,20 @@ struct gpu_ops {
u64 num_ops);
const struct regop_offset_range* (
*get_global_whitelist_ranges)(void);
int (*get_global_whitelist_ranges_count)(void);
u64 (*get_global_whitelist_ranges_count)(void);
const struct regop_offset_range* (
*get_context_whitelist_ranges)(void);
int (*get_context_whitelist_ranges_count)(void);
u64 (*get_context_whitelist_ranges_count)(void);
const u32* (*get_runcontrol_whitelist)(void);
int (*get_runcontrol_whitelist_count)(void);
u64 (*get_runcontrol_whitelist_count)(void);
const struct regop_offset_range* (
*get_runcontrol_whitelist_ranges)(void);
int (*get_runcontrol_whitelist_ranges_count)(void);
u64 (*get_runcontrol_whitelist_ranges_count)(void);
const u32* (*get_qctl_whitelist)(void);
int (*get_qctl_whitelist_count)(void);
u64 (*get_qctl_whitelist_count)(void);
const struct regop_offset_range* (
*get_qctl_whitelist_ranges)(void);
int (*get_qctl_whitelist_ranges_count)(void);
u64 (*get_qctl_whitelist_ranges_count)(void);
int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
} regops;
struct {