gpu: nvgpu: add setup_hw HAL for pbdma

Add the following HAL
- pbdma.setup_hw

This HAL takes care of setting up pbdma timeout.

Jira NVGPU-2950

Change-Id: I966d52efcd8d199c5aa5d248c7152fc47be7a431
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093000
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -442,6 +442,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.init_info = vgpu_fifo_init_engine_info,
 	},
 	.pbdma = {
+		.setup_hw = NULL,
 		.intr_enable = NULL,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -526,6 +526,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.init_info = vgpu_fifo_init_engine_info,
 	},
 	.pbdma = {
+		.setup_hw = NULL,
 		.intr_enable = NULL,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -70,8 +70,6 @@
 int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 {
 	u32 timeout;
-	unsigned int i;
-	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
 
 	nvgpu_log_fn(g, " ");
 
@@ -88,14 +86,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 	nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
 	gk20a_writel(g, fifo_fb_timeout_r(), timeout);
 
-	/* write pbdma timeout value */
-	for (i = 0; i < host_num_pbdma; i++) {
-		timeout = gk20a_readl(g, pbdma_timeout_r(i));
-		timeout = set_field(timeout, pbdma_timeout_period_m(),
-				    pbdma_timeout_period_max_f());
-		nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", timeout);
-		gk20a_writel(g, pbdma_timeout_r(i), timeout);
-	}
+	g->ops.pbdma.setup_hw(g);
 
 	g->ops.fifo.intr_0_enable(g, true);
 	g->ops.fifo.intr_1_enable(g, true);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -660,6 +660,7 @@ static const struct gpu_ops gm20b_ops = {
 		.init_ce_info = gm20b_engine_init_ce_info,
 	},
 	.pbdma = {
+		.setup_hw = gm20b_pbdma_setup_hw,
 		.intr_enable = gm20b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gm20b_pbdma_get_signature,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -748,6 +748,7 @@ static const struct gpu_ops gp10b_ops = {
 		.init_ce_info = gp10b_engine_init_ce_info,
 	},
 	.pbdma = {
+		.setup_hw = gm20b_pbdma_setup_hw,
 		.intr_enable = gm20b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -932,6 +932,7 @@ static const struct gpu_ops gv100_ops = {
 		.init_ce_info = gp10b_engine_init_ce_info,
 	},
 	.pbdma = {
+		.setup_hw = gm20b_pbdma_setup_hw,
 		.intr_enable = gv11b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -907,8 +907,6 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
 int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 {
 	u32 timeout;
-	unsigned int i;
-	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
 
 	nvgpu_log_fn(g, " ");
 
@@ -933,18 +931,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 		gk20a_writel(g, fifo_fb_timeout_r(), timeout);
 	}
 
-	for (i = 0; i < host_num_pbdma; i++) {
-		timeout = gk20a_readl(g, pbdma_timeout_r(i));
-		nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x",
-						 timeout);
-		if (!nvgpu_platform_is_silicon(g)) {
-			timeout = set_field(timeout, pbdma_timeout_period_m(),
-					pbdma_timeout_period_max_f());
-			nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x",
-						 timeout);
-			gk20a_writel(g, pbdma_timeout_r(i), timeout);
-		}
-	}
+	g->ops.pbdma.setup_hw(g);
 
 	g->ops.fifo.intr_0_enable(g, true);
 	g->ops.fifo.intr_1_enable(g, true);

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -887,6 +887,7 @@ static const struct gpu_ops gv11b_ops = {
 		.init_ce_info = gp10b_engine_init_ce_info,
 	},
 	.pbdma = {
+		.setup_hw = gv11b_pbdma_setup_hw,
 		.intr_enable = gv11b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c

@@ -484,3 +484,17 @@ void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
 	}
 #endif
 }
+
+void gm20b_pbdma_setup_hw(struct gk20a *g)
+{
+	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+	u32 i, timeout;
+
+	for (i = 0U; i < host_num_pbdma; i++) {
+		timeout = nvgpu_readl(g, pbdma_timeout_r(i));
+		timeout = set_field(timeout, pbdma_timeout_period_m(),
+				    pbdma_timeout_period_max_f());
+		nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", timeout);
+		nvgpu_writel(g, pbdma_timeout_r(i), timeout);
+	}
+}

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h

@@ -54,5 +54,6 @@ void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
 void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
 		     struct gk20a_debug_output *o,
 		     struct nvgpu_channel_dump_info *info);
+void gm20b_pbdma_setup_hw(struct gk20a *g);
 
 #endif /* NVGPU_PBDMA_GM20B_H */

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.c

@@ -25,6 +25,7 @@
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/soc.h>
 
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 
@@ -233,3 +234,22 @@ u32 gv11b_pbdma_channel_fatal_0_intr_descs(void)
 
 	return channel_fatal_0_intr_descs;
 }
+
+void gv11b_pbdma_setup_hw(struct gk20a *g)
+{
+	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+	u32 i, timeout;
+
+	for (i = 0U; i < host_num_pbdma; i++) {
+		timeout = nvgpu_readl(g, pbdma_timeout_r(i));
+		nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x",
+						 timeout);
+		if (!nvgpu_platform_is_silicon(g)) {
+			timeout = set_field(timeout, pbdma_timeout_period_m(),
+					pbdma_timeout_period_max_f());
+			nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x",
+						 timeout);
+			nvgpu_writel(g, pbdma_timeout_r(i), timeout);
+		}
+	}
+}

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h

@@ -27,6 +27,7 @@
 
 struct gk20a;
 
+void gv11b_pbdma_setup_hw(struct gk20a *g);
 void gv11b_pbdma_intr_enable(struct gk20a *g, bool enable);
 bool gv11b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
 			u32 *error_notifier);

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1073,6 +1073,7 @@ struct gpu_ops {
 	} engine;
 
 	struct {
+		void (*setup_hw)(struct gk20a *g);
 		void (*intr_enable)(struct gk20a *g, bool enable);
 		bool (*handle_intr_0)(struct gk20a *g,
 				u32 pbdma_id, u32 pbdma_intr_0,

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -966,6 +966,7 @@ static const struct gpu_ops tu104_ops = {
 		.init_ce_info = gp10b_engine_init_ce_info,
 	},
 	.pbdma = {
+		.setup_hw = gv11b_pbdma_setup_hw,
 		.intr_enable = gv11b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,