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gpu: nvgpu: fixes for tu104 usermode register write
- correct user register base l->usermode_regs. It should be bar0 address plus .usermode.bus_base(). .bus_base() returns user register base offset relative to bar0. - correct .usermode.base for tu104. .base should be user register base relative to virtual function base. - use nvgpu_usermode_writel for tu104 ring doorbell. Jira GVSCI-4650 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: Iba98063c4a5cc007459319b0311e546ff10604a4 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2403813 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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committed by
Alex Waterman
parent
a2809088eb
commit
2dfa05ba50
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -60,7 +60,7 @@ void nvgpu_init_usermode_support(struct gk20a *g)
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}
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if (l->usermode_regs == NULL) {
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l->usermode_regs = l->regs + g->ops.usermode.base(g);
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l->usermode_regs = l->regs + g->ops.usermode.bus_base(g);
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l->usermode_regs_saved = l->usermode_regs;
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}
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