gpu: nvgpu: fixes for tu104 usermode register write

- correct user register base l->usermode_regs. It should be bar0 address
plus .usermode.bus_base(). .bus_base() returns user register base offset
relative to bar0.
- correct .usermode.base for tu104. .base should be user register base
relative to virtual function base.
- use nvgpu_usermode_writel for tu104 ring doorbell.

Jira GVSCI-4650

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Iba98063c4a5cc007459319b0311e546ff10604a4
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2403813
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2020-08-25 16:13:42 -07:00
committed by Alex Waterman
parent a2809088eb
commit 2dfa05ba50
2 changed files with 6 additions and 5 deletions

View File

@@ -25,6 +25,7 @@
#include <nvgpu/log.h> #include <nvgpu/log.h>
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/channel.h> #include <nvgpu/channel.h>
#include <nvgpu/io_usermode.h>
#include "usermode_tu104.h" #include "usermode_tu104.h"
@@ -34,7 +35,7 @@
u64 tu104_usermode_base(struct gk20a *g) u64 tu104_usermode_base(struct gk20a *g)
{ {
return usermode_cfg0_r(); return func_cfg0_r();
} }
u64 tu104_usermode_bus_base(struct gk20a *g) u64 tu104_usermode_bus_base(struct gk20a *g)
@@ -66,6 +67,6 @@ void tu104_usermode_ring_doorbell(struct nvgpu_channel *ch)
nvgpu_log_info(ch->g, "channel ring door bell %d, runlist %d", nvgpu_log_info(ch->g, "channel ring door bell %d, runlist %d",
ch->chid, ch->runlist_id); ch->chid, ch->runlist_id);
nvgpu_func_writel(ch->g, func_doorbell_r(), nvgpu_usermode_writel(ch->g, func_doorbell_r(),
tu104_usermode_doorbell_token(ch)); ch->g->ops.usermode.doorbell_token(ch));
} }

View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -60,7 +60,7 @@ void nvgpu_init_usermode_support(struct gk20a *g)
} }
if (l->usermode_regs == NULL) { if (l->usermode_regs == NULL) {
l->usermode_regs = l->regs + g->ops.usermode.base(g); l->usermode_regs = l->regs + g->ops.usermode.bus_base(g);
l->usermode_regs_saved = l->usermode_regs; l->usermode_regs_saved = l->usermode_regs;
} }