gpu: nvgpu: move mc gpu_ops out of gk20a.h and add doxygen comments for HALs

gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.

JIRA NVGPU-2524

Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-common.yaml

@@ -112,7 +112,8 @@ mc:
   safe: yes
   owner: Seema K
   sources: [ common/mc/mc.c,
-             include/nvgpu/mc.h ]
+             include/nvgpu/mc.h,
+             include/nvgpu/gops_mc.h ]
 class:
   safe: yes
   owner: Seshendra G

drivers/gpu/nvgpu/common/ce/ce.c

@@ -25,6 +25,7 @@
 #include <nvgpu/engines.h>
 #include <nvgpu/ce.h>
 #include <nvgpu/power_features/cg.h>
+#include <nvgpu/gops_mc.h>
 
 int nvgpu_ce_init_support(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/fifo/engines.c

@@ -42,6 +42,7 @@
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/static_analysis.h>
+#include <nvgpu/gops_mc.h>
 
 #define FECS_METHOD_WFI_RESTORE	0x80000U
 

drivers/gpu/nvgpu/common/gr/gr.c

@@ -42,6 +42,7 @@
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include "gr_priv.h"
 

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -35,6 +35,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel_sync.h>
 #include <nvgpu/nvgpu_init.h>
+#include <nvgpu/gops_mc.h>
 
 #ifdef CONFIG_NVGPU_TRACE
 #include <trace/events/gk20a.h>

drivers/gpu/nvgpu/common/mm/mm.c

@@ -35,6 +35,7 @@
 #include <nvgpu/engines.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/power_features/cg.h>
+#include <nvgpu/gops_mc.h>
 
 int nvgpu_mm_suspend(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c

@@ -34,6 +34,8 @@
 #include <nvgpu/top.h>
 #include <nvgpu/nvlink_minion.h>
 #include <nvgpu/nvlink_link_mode_transitions.h>
+#include <nvgpu/gops_mc.h>
+
 #include "nvlink_gv100.h"
 
 #include <nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h>

drivers/gpu/nvgpu/hal/fb/fb_gv100.c

@@ -40,6 +40,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include "fb_gv100.h"
 

drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c

@@ -28,6 +28,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include "hal/fifo/fifo_gk20a.h"
 

drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c

@@ -30,6 +30,7 @@
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 

drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c

@@ -39,6 +39,7 @@
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/mutex.h>
 #endif
+#include <nvgpu/gops_mc.h>
 
 #include "preempt_gv11b.h"
 

drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c

@@ -44,6 +44,7 @@
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/hwpm_map.h>
 #include <nvgpu/preempt.h>
+#include <nvgpu/gops_mc.h>
 
 #include "gr_gk20a.h"
 #include "gr_pri_gk20a.h"

drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c

@@ -43,6 +43,7 @@
 #include <nvgpu/engine_status.h>
 #include <nvgpu/fbp.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/gops_mc.h>
 
 #include "gr_pri_gk20a.h"
 #include "gr_pri_gv11b.h"

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -960,7 +960,9 @@ static const struct gpu_ops gm20b_ops = {
 	.mc = {
 		.intr_mask = gm20b_mc_intr_mask,
 		.intr_enable = gm20b_mc_intr_enable,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = gm20b_mc_intr_pmu_unit_config,
+#endif
 		.isr_stall = gm20b_mc_isr_stall,
 		.intr_stall = gm20b_mc_intr_stall,
 		.intr_stall_pause = gm20b_mc_intr_stall_pause,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -1056,7 +1056,9 @@ static const struct gpu_ops gp10b_ops = {
 	.mc = {
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gp10b_intr_enable,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
+#endif
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = mc_gp10b_intr_stall,
 		.intr_stall_pause = mc_gp10b_intr_stall_pause,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1259,7 +1259,9 @@ static const struct gpu_ops gv11b_ops = {
 	.mc = {
 		.intr_mask = mc_gp10b_intr_mask,
 		.intr_enable = mc_gv11b_intr_enable,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
+#endif
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = mc_gp10b_intr_stall,
 		.intr_stall_pause = mc_gp10b_intr_stall_pause,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1276,7 +1276,9 @@ static const struct gpu_ops tu104_ops = {
 	.mc = {
 		.intr_enable = intr_tu104_enable,
 		.intr_mask = intr_tu104_mask,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = mc_gp10b_intr_pmu_unit_config,
+#endif
 		.isr_stall = mc_gp10b_isr_stall,
 		.intr_stall = intr_tu104_stall,
 		.intr_stall_pause = intr_tu104_stall_pause,

drivers/gpu/nvgpu/hal/mc/mc_gm20b.c

@@ -31,6 +31,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/power_features/pg.h>
+#include <nvgpu/gops_mc.h>
 
 #include "mc_gm20b.h"
 

drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c

@@ -31,6 +31,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/power_features/pg.h>
+#include <nvgpu/gops_mc.h>
 
 #include "mc_gm20b.h"
 
@@ -133,9 +134,11 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 	case NVGPU_UNIT_BLG:
 		mask = mc_enable_blg_enabled_f();
 		break;
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	case NVGPU_UNIT_PWR:
 		mask = mc_enable_pwr_enabled_f();
 		break;
+#endif
 	default:
 		WARN(true, "unknown reset unit %d", unit);
 		break;

drivers/gpu/nvgpu/hal/mc/mc_gp10b.c

@@ -61,3 +61,26 @@ int mc_gp10b_intr_enable(struct gk20a *g)
 
 	return 0;
 }
+
+void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable)
+{
+	u32 reg = 0U;
+
+	if (enable) {
+		reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
+			mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
+
+	} else {
+		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
+			~mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
+
+		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
+		g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
+			~mc_intr_pmu_pending_f();
+		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
+	}
+}

drivers/gpu/nvgpu/hal/mc/mc_gp10b.h

@@ -31,7 +31,6 @@ struct gk20a;
 enum nvgpu_unit;
 
 void mc_gp10b_intr_mask(struct gk20a *g);
-void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable);
 void mc_gp10b_isr_stall(struct gk20a *g);
 bool mc_gp10b_is_intr1_pending(struct gk20a *g,
 				      enum nvgpu_unit unit, u32 mc_intr_1);
@@ -45,6 +44,10 @@ void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
 void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
 void mc_gp10b_ltc_isr(struct gk20a *g);
 
+#ifdef CONFIG_NVGPU_LS_PMU
+void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable);
+#endif
+
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 int mc_gp10b_intr_enable(struct gk20a *g);
 #endif

drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c

@@ -28,6 +28,7 @@
 #include <nvgpu/ltc.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/power_features/pg.h>
+#include <nvgpu/gops_mc.h>
 
 #include "mc_gp10b.h"
 
@@ -44,29 +45,6 @@ void mc_gp10b_intr_mask(struct gk20a *g)
 				U32_MAX);
 }
 
-void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable)
-{
-	u32 reg = 0U;
-
-	if (enable) {
-		reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
-		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
-			mc_intr_pmu_pending_f();
-		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
-
-	} else {
-		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
-		g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
-			~mc_intr_pmu_pending_f();
-		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
-
-		reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
-		g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
-			~mc_intr_pmu_pending_f();
-		nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
-	}
-}
-
 static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 {
 	if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
@@ -75,6 +53,7 @@ static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
 		g->ops.bus.isr(g);
 	}
+#ifdef CONFIG_NVGPU_DGPU
 	if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
 			g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
 		g->ops.nvlink.intr.isr(g);
@@ -83,6 +62,7 @@ static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 			(g->ops.mc.fbpa_isr != NULL)) {
 		g->ops.mc.fbpa_isr(g);
 	}
+#endif
 }
 
 

drivers/gpu/nvgpu/hal/mc/mc_tu104.c

@@ -27,6 +27,7 @@
 #include <nvgpu/ltc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engines.h>
+#include <nvgpu/gops_mc.h>
 
 #include "hal/mc/mc_gp10b.h"
 

drivers/gpu/nvgpu/hal/perf/perf_gm20b.c

@@ -25,6 +25,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include "perf_gm20b.h"
 

drivers/gpu/nvgpu/hal/perf/perf_gv11b.c

@@ -25,6 +25,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include "perf_gv11b.h"
 

drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c

@@ -30,6 +30,7 @@
 #include <nvgpu/pmu/debug.h>
 #include <nvgpu/pmu/pmu_pg.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/gops_mc.h>
 
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
 

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c

@@ -753,7 +753,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	.mc = {
 		.intr_mask = NULL,
 		.intr_enable = NULL,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = NULL,
+#endif
 		.isr_stall = NULL,
 		.intr_stall = NULL,
 		.intr_stall_pause = NULL,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -875,7 +875,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	.mc = {
 		.intr_mask = NULL,
 		.intr_enable = NULL,
+#ifdef CONFIG_NVGPU_LS_PMU
 		.intr_pmu_unit_config = NULL,
+#endif
 		.isr_stall = NULL,
 		.intr_stall = NULL,
 		.intr_stall_pause = NULL,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -160,6 +160,7 @@ enum nvgpu_unit;
 #include <nvgpu/gops_priv_ring.h>
 #include <nvgpu/gops_therm.h>
 #include <nvgpu/gops_fb.h>
+#include <nvgpu/gops_mc.h>
 
 #include "hal/clk/clk_gk20a.h"
 
@@ -512,35 +513,8 @@ struct gpu_ops {
 		u64 (*get_qctl_whitelist_count)(void);
 	} regops;
 #endif
-	struct {
-		void (*intr_mask)(struct gk20a *g);
-		int (*intr_enable)(struct gk20a *g);
-		void (*intr_pmu_unit_config)(struct gk20a *g,
-				bool enable);
-		void (*isr_stall)(struct gk20a *g);
-		bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
-		bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
-		bool (*is_stall_and_eng_intr_pending)(struct gk20a *g,
-					u32 act_eng_id, u32 *eng_intr_pending);
-		u32 (*intr_stall)(struct gk20a *g);
-		void (*intr_stall_pause)(struct gk20a *g);
-		void (*intr_stall_resume)(struct gk20a *g);
-		u32 (*intr_nonstall)(struct gk20a *g);
-		void (*intr_nonstall_pause)(struct gk20a *g);
-		void (*intr_nonstall_resume)(struct gk20a *g);
-		u32 (*isr_nonstall)(struct gk20a *g);
-		void (*enable)(struct gk20a *g, u32 units);
-		void (*disable)(struct gk20a *g, u32 units);
-		void (*reset)(struct gk20a *g, u32 units);
-		bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
-		bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
-		void (*log_pending_intrs)(struct gk20a *g);
-		void (*fbpa_isr)(struct gk20a *g);
-		u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
-		void (*fb_reset)(struct gk20a *g);
-		void (*ltc_isr)(struct gk20a *g);
-		bool (*is_mmu_fault_pending)(struct gk20a *g);
-	} mc;
+	struct gops_mc mc;
+
 	struct {
 		void (*show_dump)(struct gk20a *g,
 				struct nvgpu_debug_context *o);

drivers/gpu/nvgpu/include/nvgpu/gops_mc.h

@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_GOPS_MC_H
+#define NVGPU_GOPS_MC_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/mc.h>
+
+/**
+ * @file
+ *
+ * MC HAL interface.
+ */
+struct gk20a;
+
+/**
+ * MC HAL operations.
+ *
+ * @see gpu_ops.
+ */
+struct gops_mc {
+	/**
+	 * @brief Clear the GPU device interrupts at master level.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked before powering off or finishing
+	 * SW quiesce of nvgpu driver.
+	 *
+	 * Steps:
+	 * - Write U32_MAX to the stalling interrupts enable clear register.
+	 *   mc_intr_en_clear_r are write only registers which clear
+	 *   the corresponding bit in INTR_EN whenever a 1 is written
+	 *   to it.
+	 * - Write U32_MAX to the non-stalling interrupts enable clear register.
+	 */
+	void (*intr_mask)(struct gk20a *g);
+
+	/**
+	 * @brief Enable the applicable GPU device interrupts at master level.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked during #nvgpu_finalize_poweron before
+	 * enabling the individual HW units interrupts.
+	 *
+	 * Steps:
+	 * - Get the engine interrupts mask for supported FIFO engines by
+	 *   calling #nvgpu_engine_interrupt_mask.
+	 * - Clear the GPU device interrupts.
+	 * - Set the master level interrupts masks to be used for
+	 *   enabling/disabling the interrupts at runtime in
+	 *   #intr_stall_pause, #intr_stall_resume,
+	 *   #intr_nonstall_pause and #intr_nonstall_resume.
+	 *   - Initialize the stalling interrupts bitmask
+	 *     #mc_intr_mask_restore[#NVGPU_MC_INTR_STALLING] with various
+	 *     units (FIFO, HUB, PRIV_RING, PBUS, LTC) OR'ing with engine
+	 *     interrupts mask.
+	 *   - Initialize the non-stalling interrupts bitmask
+	 *     #mc_intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING] with FIFO
+	 *     unit OR'ing with engine interrupts mask.
+	 * - Write the bitmasks to the stalling and the non-stalling interrupts
+	 *   enable registers respectively (mc_intr_en_set_r()).
+	 *
+	 * @return 0 in case of success, < 0 in case of failure.
+	 */
+	int (*intr_enable)(struct gk20a *g);
+
+	/**
+	 * @brief Read the the stalling interrupts status register.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to get the stalling interrupts reported
+	 * by the GPU before invoking the ISR.
+	 *
+	 * Steps:
+	 * - Read and return the value of the register
+	 *   mc_intr_r(#NVGPU_MC_INTR_STALLING).
+	 *
+	 * @return value read from mc_intr_r(#NVGPU_MC_INTR_STALLING).
+	 */
+	u32 (*intr_stall)(struct gk20a *g);
+
+	/**
+	 * @brief Disable/Pause the stalling interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to disable the stalling interrupts before
+	 * the ISR is executed.
+	 *
+	 * Steps:
+	 * - Write U32_MAX to the stalling interrupts enable clear register
+	 *   (mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING)).
+	 */
+	void (*intr_stall_pause)(struct gk20a *g);
+
+	/**
+	 * @brief Interrupt Service Routine (ISR) for handling the stalling
+	 *        interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is called by OS interrupt unit on receiving
+	 * stalling interrupt for servicing it.
+	 *
+	 * Steps:
+	 * - Read mc_intr_r(#NVGPU_MC_INTR_STALLING) register to get the
+	 *   stalling interrupts reported.
+	 * - For the FIFO engines with pending interrupt invoke corresponding
+	 *   handlers.
+	 *   - Invoke g->ops.gr.intr.stall_isr if GR interrupt is pending.
+	 *   - Invoke g->ops.ce.isr_stall if CE interrupt is pending.
+	 * - For other units with pending interrupt invoke corresponding
+	 *   handlers.
+	 *   - Invoke g->ops.fb.intr.isr if HUB interrupt is pending, determined
+	 *     by calling g->ops.mc.is_intr_hub_pending.
+	 *   - Invoke g->ops.fifo.intr_0_isr if FIFO interrupt is pending. The
+	 *     FIFO interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
+	 *     mc_intr_pfifo_pending_f.
+	 *   - Invoke g->ops.priv_ring.isr if PRIV_RING interrupt is pending.
+	 *     The PRIV_RING interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING)
+	 *     is mc_intr_priv_ring_pending_f.
+	 *   - Invoke g->ops.mc.ltc_isr if LTC interrupt is pending. The
+	 *     LTC interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
+	 *     mc_intr_ltc_pending_f.
+	 *   - Invoke g->ops.bus.isr if BUS interrupt is pending. The
+	 *     BUS interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
+	 *     mc_intr_pbus_pending_f.
+	 */
+	void (*isr_stall)(struct gk20a *g);
+
+	/**
+	 * @brief Enable/Resume the stalling interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to enable the stalling interrupts after
+	 * the ISR is executed.
+	 *
+	 * Steps:
+	 * - Enable the stalling interrupts as configured during #intr_enable.
+	 *   Write #mc_intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the
+	 *   stalling interrupts enable set register
+	 *   (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
+	 */
+	void (*intr_stall_resume)(struct gk20a *g);
+
+	/**
+	 * @brief Read the non-stalling interrupts status register.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to get the non-stalling interrupts reported
+	 * by the GPU before invoking the ISR.
+	 *
+	 * Steps:
+	 * - Read and return the value of the register
+	 *   mc_intr_r(#NVGPU_MC_INTR_NONSTALLING).
+	 *
+	 * @return value read from mc_intr_r(#NVGPU_MC_INTR_NONSTALLING).
+	 */
+	u32 (*intr_nonstall)(struct gk20a *g);
+
+	/**
+	 * @brief Disable/Pause the non-stalling interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to disable the non-stalling interrupts
+	 * before the ISR is executed.
+	 *
+	 * Steps:
+	 * - Write U32_MAX to the non-stalling interrupts enable clear register
+	 *   (mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING)).
+	 */
+	void (*intr_nonstall_pause)(struct gk20a *g);
+
+	/**
+	 * @brief Interrupt Service Routine (ISR) for handling the non-stalling
+	 *        interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is called by OS interrupt unit on receiving
+	 * non-stalling interrupt for servicing it.
+	 *
+	 * Steps:
+	 * - Read mc_intr_r(#NVGPU_MC_INTR_NONSTALLING) register to get the
+	 *   non-stalling interrupts reported.
+	 * - Invoke g->ops.fifo.intr_1_isr if FIFO non-stalling interrupt
+	 *   is pending, determined by calling mc_intr_pfifo_pending_f.
+	 * - For the FIFO engines with pending interrupt invoke corresponding
+	 *   handlers.
+	 *   - Invoke g->ops.gr.intr.nonstall_isr if GR interrupt is pending.
+	 *   - Invoke g->ops.ce.isr_nonstall if CE interrupt is pending.
+	 *   These functions return bitmask of operations that are executed on
+	 *   non-stall workqueue.
+	 *
+	 * @return bitmask of operations that are executed on non-stall
+	 * workqueue.
+	 */
+	u32 (*isr_nonstall)(struct gk20a *g);
+
+	/**
+	 * @brief Enable/Resume the non-stalling interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to enable the non-stalling interrupts after
+	 * the ISR is executed.
+	 *
+	 * Steps:
+	 * - Enable the non-stalling interrupts as configured during
+	 *   #intr_enable.
+	 *   Write #mc_intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
+	 *   to the non-stalling interrupts enable set register
+	 *   (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
+	 */
+	void (*intr_nonstall_resume)(struct gk20a *g);
+
+	/**
+	 * @brief Check if stalling or engine interrupts are pending.
+	 *
+	 * @param g [in]			The GPU driver struct.
+	 * @param act_eng_id [in]		Active engine id.
+	 * @param eng_intr_pending [out]	Indicates if engine interrupt
+	 *					is pending.
+	 *
+	 * This function is invoked while polling for preempt completion.
+	 *
+	 * Steps:
+	 * - Read mc_intr_r(#NVGPU_MC_INTR_STALLING) register to get
+	 *   the interrupts reported.
+	 * - Get the engine interrupt mask corresponding to \a act_eng_id.
+	 * - Check if the bits for engine interrupt mask are set in the
+	 *   mc_intr_r(#NVGPU_MC_INTR_STALLING) register by AND'ing values
+	 *   read in above two steps. Store the result in \a eng_intr_pending.
+	 * - Initialize the stalling interrupt mask with bitmask for FIFO, HUB,
+	 *   PRIV_RING, PBUS, LTC unit interrupts.
+	 * - Return true if bits from above stalling interrupt mask or the
+	 *   engine interrupt mask are set in the
+	 *   mc_intr_r(#NVGPU_MC_INTR_STALLING) register. Else, return false.
+	 *
+	 * @return true if stalling or engine interrupt is pending, else false.
+	 */
+	bool (*is_stall_and_eng_intr_pending)(struct gk20a *g,
+				u32 act_eng_id, u32 *eng_intr_pending);
+
+	/**
+	 * @brief Reset the HW unit/engine.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 * @param units [in]	Bitmask of values designating GPU HW engines
+	 *			controlled by MC. This is used to update bits in
+	 *			the mc_enable_r register.
+	 *			- Supported values are:
+	 *			  - #NVGPU_UNIT_FIFO
+	 *			  - #NVGPU_UNIT_PERFMON
+	 *			  - #NVGPU_UNIT_GRAPH
+	 *			  - #NVGPU_UNIT_BLG
+	 *			  - Reset id of supported engines from the
+	 *                          device info. For e.g. GR engine has reset
+	 *                          id of 12. @see #nvgpu_device_info.
+	 *
+	 * This function is invoked to reset the engines while initializing
+	 * FIFO, GR and other engines during #nvgpu_finalize_poweron.
+	 *
+	 * Steps:
+	 * - Disable the HW unit/engine.
+	 *   - Acquire g->mc_enable_lock spinlock.
+	 *   - Read mc_enable_r register and clear the bits in the read value
+	 *     corresponding to HW unit to be disabled.
+	 *   - Write mc_enable_r with the updated value.
+	 *   - Release g->mc_enable_lock spinlock.
+	 * - Sleep/wait for 500us if resetting CE engines else sleep for 20us.
+	 * - Enable the HW unit/engine.
+	 *   - Acquire g->mc_enable_lock spinlock.
+	 *   - Read mc_enable_r register and set the bits in the read value
+	 *     corresponding to HW unit to be disabled.
+	 *   - Write mc_enable_r with the updated value.
+	 *   - Read back mc_enable_r.
+	 *   - Release g->mc_enable_lock spinlock.
+	 *   - Sleep/wait for 20us.
+	 */
+	void (*reset)(struct gk20a *g, u32 units);
+
+	/**
+	 * @brief Get the reset mask for the HW unit/engine.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 * @param unit [in]	Value designating the GPU HW unit/engine
+	 *                      controlled by MC. Supported values are:
+	 *			  - NVGPU_UNIT_FIFO
+	 *			  - NVGPU_UNIT_PERFMON
+	 *			  - NVGPU_UNIT_GRAPH
+	 *			  - NVGPU_UNIT_BLG
+	 *
+	 * This function is invoked to get the reset mask of the engines for
+	 * resetting CE, GR, FIFO during #nvgpu_finalize_poweron.
+	 *
+	 * Steps:
+	 * - If \a unit is #NVGPU_UNIT_FIFO, return mc_enable_pfifo_enabled_f.
+	 * - else if \a unit is #NVGPU_UNIT_PERFMON,
+	 *   return mc_enable_perfmon_enabled_f.
+	 * - else if \a unit is #NVGPU_UNIT_GRAPH,
+	 *   return mc_enable_pgraph_enabled_f.
+	 * - else if \a unit is #NVGPU_UNIT_BLG, return mc_enable_blg_enabled_f.
+	 * - else return 0.
+	 *
+	 * @return bitmask corresponding to supported engines, else 0.
+	 */
+	u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
+
+	/**
+	 * @brief Interrupt Service Routine (ISR) for handling the Level Two
+	 *        Cache (LTC) interrupts.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * This function is invoked to handle the LTC interrupts from
+	 * #isr_stall.
+	 *
+	 * Steps:
+	 * - Read mc_intr_ltc_r register to get the interrupts status for LTCs.
+	 * - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g)
+	 *   - If interrupt bitmask is set in the interrupts status register
+	 *     - Invoke g->ops.ltc.intr.isr.
+	 */
+	void (*ltc_isr)(struct gk20a *g);
+
+	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
+
+	void (*enable)(struct gk20a *g, u32 units);
+
+	void (*disable)(struct gk20a *g, u32 units);
+
+	bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
+
+	bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit,
+				 u32 mc_intr_1);
+
+	bool (*is_mmu_fault_pending)(struct gk20a *g);
+
+	bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
+
+	void (*log_pending_intrs)(struct gk20a *g);
+
+	void (*fb_reset)(struct gk20a *g);
+
+#ifdef CONFIG_NVGPU_DGPU
+	bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
+	void (*fbpa_isr)(struct gk20a *g);
+#endif
+
+#ifdef CONFIG_NVGPU_LS_PMU
+	void (*intr_pmu_unit_config)(struct gk20a *g,
+			bool enable);
+#endif
+	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
+};
+
+#endif

drivers/gpu/nvgpu/include/nvgpu/mc.h

@@ -38,8 +38,12 @@ enum nvgpu_unit {
 	NVGPU_UNIT_PERFMON,
 	NVGPU_UNIT_GRAPH,
 	NVGPU_UNIT_BLG,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	NVGPU_UNIT_PWR,
+#endif
+#ifdef CONFIG_NVGPU_DGPU
 	NVGPU_UNIT_NVDEC,
+#endif
 };
 
 #define NVGPU_MC_INTR_STALLING		0U

drivers/gpu/nvgpu/os/linux/intr.c

@@ -19,6 +19,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/nvgpu_init.h>
+#include <nvgpu/gops_mc.h>
 
 #include <nvgpu/atomic.h>
 #include "os_linux.h"

userspace/units/init/nvgpu-init.c

@@ -31,6 +31,7 @@
 #include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
 #include <nvgpu/posix/posix-fault-injection.h>
 #include <nvgpu/dma.h>
+#include <nvgpu/gops_mc.h>
 
 #include "nvgpu-init.h"
 

userspace/units/mm/mm/mm.c

@@ -27,6 +27,8 @@
 
 #include <nvgpu/nvgpu_init.h>
 #include <nvgpu/posix/io.h>
+#include <nvgpu/gops_mc.h>
+
 #include "os/posix/os_posix.h"
 
 #include "hal/mm/mm_gp10b.h"

userspace/units/mm/page_table_faults/page_table_faults.c

@@ -34,6 +34,8 @@
 #include <nvgpu/vm.h>
 #include <nvgpu/nvgpu_sgt.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/gops_mc.h>
+
 #include "os/posix/os_posix.h"
 #include "hal/fifo/channel_gv11b.h"