From 2f1d251d79659307dcf076db72e5f275b48282d7 Mon Sep 17 00:00:00 2001 From: Nicolas Benech Date: Wed, 16 Oct 2019 17:20:20 -0400 Subject: [PATCH] gpu: nvgpu: doxygen: fix param syntax Doxygen requires a space between in/out qualifiers and the parameter name. This patch fixes 500+ occurences of the issue. JIRA NVGPU-4120 Change-Id: Iaa3a7c69e1bed9b528796b669e11a2f13aa63301 Signed-off-by: Nicolas Benech Reviewed-on: https://git-master.nvidia.com/r/2219641 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/channel.h | 126 +++++++++--------- .../gpu/nvgpu/include/nvgpu/engine_status.h | 28 ++-- drivers/gpu/nvgpu/include/nvgpu/engines.h | 74 +++++----- drivers/gpu/nvgpu/include/nvgpu/fifo.h | 16 +-- drivers/gpu/nvgpu/include/nvgpu/gr/config.h | 96 ++++++------- drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h | 118 ++++++++-------- drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h | 4 +- .../gpu/nvgpu/include/nvgpu/gr/global_ctx.h | 70 +++++----- drivers/gpu/nvgpu/include/nvgpu/gr/gr.h | 36 ++--- .../gpu/nvgpu/include/nvgpu/gr/gr_falcon.h | 30 ++--- drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h | 70 +++++----- drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h | 10 +- drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h | 98 +++++++------- drivers/gpu/nvgpu/include/nvgpu/gr/setup.h | 20 +-- drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h | 26 ++-- drivers/gpu/nvgpu/include/nvgpu/io_usermode.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/ltc.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pbdma.h | 10 +- .../gpu/nvgpu/include/nvgpu/pbdma_status.h | 12 +- .../nvgpu/include/nvgpu/power_features/cg.h | 26 ++-- drivers/gpu/nvgpu/include/nvgpu/preempt.h | 6 +- drivers/gpu/nvgpu/include/nvgpu/runlist.h | 70 +++++----- drivers/gpu/nvgpu/include/nvgpu/soc.h | 16 +-- drivers/gpu/nvgpu/include/nvgpu/tsg.h | 88 ++++++------ 24 files changed, 527 insertions(+), 527 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index c9c605763..747ab245a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -664,7 +664,7 @@ void nvgpu_channel_wdt_restart_all_channels(struct gk20a *g); /** * @brief Get channel pointer from its node in free channels list. * - * @param node[in] Pointer to node entry in the list of free channels. + * @param node [in] Pointer to node entry in the list of free channels. * Cannot be NULL, and must be valid. * * @return Channel pointer. @@ -679,7 +679,7 @@ nvgpu_channel_from_free_chs(struct nvgpu_list_node *node) /** * @brief Get channel pointer from its node in TSG's channel list. * - * @param node[in] Pointer to node entry in TSG's channel list. + * @param node [in] Pointer to node entry in TSG's channel list. * Cannot be NULL, and must be valid. * * Computes channel pointer from #node pointer. @@ -696,7 +696,7 @@ nvgpu_channel_from_ch_entry(struct nvgpu_list_node *node) /** * @brief Check if channel is bound to an address space. * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * @return True if channel is bound to an address space, false otherwise. */ @@ -708,7 +708,7 @@ static inline bool nvgpu_channel_as_bound(struct nvgpu_channel *ch) /** * @brief Commit channel's address space. * - * @param c[in] Channel pointer. + * @param c [in]Channel pointer. * * Once a channel is bound to an address space, this function applies * related settings to channel instance block (e.g. PDB and page size). @@ -718,8 +718,8 @@ void nvgpu_channel_commit_va(struct nvgpu_channel *c); /** * @brief Initializes channel context. * - * @param g[in] Pointer to GPU driver struct. - * @param chid[in] Channel H/W Identifier. + * @param g [in] Pointer to GPU driver struct. + * @param chid [in] Channel H/W Identifier. * * Initializes channel context to default values. * This includes mutexes and list nodes initialization. @@ -731,7 +731,7 @@ int nvgpu_channel_init_support(struct gk20a *g, u32 chid); /** * @brief Initializes channel unit. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Gets number of channels from hardware. * Allocates and initializes channel contexts. @@ -745,7 +745,7 @@ int nvgpu_channel_setup_sw(struct gk20a *g); /** * @brief De-initializes channel unit. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Forcibly closes all opened channels. * Frees all channel contexts. @@ -757,7 +757,7 @@ void nvgpu_channel_cleanup_sw(struct gk20a *g); /** * @brief Emergency quiescing of channels * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Driver has encountered uncorrectable error, and is entering * SW Quiesce state. For each channel: @@ -771,7 +771,7 @@ void nvgpu_channel_sw_quiesce(struct gk20a *g); /** * @brief Close channel * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * Unbinds channel from TSG, waits until there is no more refs to the channel, * then frees channel resources. @@ -788,7 +788,7 @@ void nvgpu_channel_close(struct nvgpu_channel *ch); /** * @brief Forcibly close a channel * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * Forcibly close a channel. It is meant for terminating channels * when we know the driver is otherwise dying. Ref counts and the like @@ -801,8 +801,8 @@ void nvgpu_channel_kill(struct nvgpu_channel *ch); /** * @brief Mark unrecoverable error for channel * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. * * An unrecoverable error occurred for the channel. Mark the channel * as unserviceable, and unblock pending waits on this channel (semaphore @@ -815,8 +815,8 @@ bool nvgpu_channel_mark_error(struct gk20a *g, struct nvgpu_channel *ch); /** * @brief Abort channel's TSG * - * @param ch[in] Channel pointer. - * @param preempt[in] True if TSG should be pre-empted + * @param ch [in] Channel pointer. + * @param preempt [in] True if TSG should be pre-empted * * Disables and optionally preempts the channel's TSG. * Afterwards, all channels in the TSG are marked as unserviceable. @@ -830,8 +830,8 @@ void nvgpu_channel_abort_clean_up(struct nvgpu_channel *ch); /** * @brief Wake up all threads waiting on semaphore wait * - * @param g[in] Pointer to GPU driver struct. - * @param post_events[in] When true, notify all threads waiting + * @param g [in] Pointer to GPU driver struct. + * @param post_events [in] When true, notify all threads waiting * on TSG events. * * Goes through all channels, and wakes up semaphore wait queue. @@ -842,8 +842,8 @@ void nvgpu_channel_semaphore_wakeup(struct gk20a *g, bool post_events); /** * @brief Enable all channels in channel's TSG * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. * * Enables all channels that are in the same TSG as #ch. * @@ -855,8 +855,8 @@ int nvgpu_channel_enable_tsg(struct gk20a *g, struct nvgpu_channel *ch); /** * @brief Disables all channels in channel's TSG * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. * * Disables all channels that are in the same TSG as #ch. * A disable channel is never scheduled to run, even if it is @@ -870,7 +870,7 @@ int nvgpu_channel_disable_tsg(struct gk20a *g, struct nvgpu_channel *ch); /** * @brief Suspend all serviceable channels * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function is typically called when preparing power off. * It disables and preempts all active TSGs, then unbinds all channels contexts @@ -884,7 +884,7 @@ int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g); /** * @brief Resume all serviceable channels * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Bind all serviceable channels contexts back to hardware. * @@ -895,7 +895,7 @@ int nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g); /** * @brief Stop deterministic channel activity for do_idle(). * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Stop deterministic channel activity for do_idle() when power needs to go off * momentarily but deterministic channels keep power refs for potentially a @@ -910,7 +910,7 @@ void nvgpu_channel_deterministic_idle(struct gk20a *g); /** * @brief Allow deterministic channel activity again for do_unidle(). * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Releases exclusive access to allow again new deterministic submits, then * walks through deterministic channels to take back power refs. @@ -922,8 +922,8 @@ void nvgpu_channel_deterministic_unidle(struct gk20a *g); /** * @brief Get a reference to the channel. * - * @param ch[in] Channel pointer. - * @param caller[in] Caller function name (for reference tracking). + * @param ch [in] Channel pointer. + * @param caller [in] Caller function name (for reference tracking). * * Always when a nvgpu_channel pointer is seen and about to be used, a * reference must be held to it - either by you or the caller, which should be @@ -943,8 +943,8 @@ struct nvgpu_channel *nvgpu_channel_get__func( /** * @brief Drop a reference to the channel. * - * @param ch[in] Channel pointer. - * @param caller[in] Caller function name (for reference tracking). + * @param ch [in] Channel pointer. + * @param caller [in] Caller function name (for reference tracking). * * Drop reference to a channel, when nvgpu_channel pointer is not used anymore. */ @@ -954,9 +954,9 @@ void nvgpu_channel_put__func(struct nvgpu_channel *ch, const char *caller); /** * @brief Get a reference to the channel by id. * - * @param g[in] Pointer to GPU driver struct. - * @param chid[in] Channel Identifier. - * @param caller[in] Caller function name (for reference tracking). + * @param g [in] Pointer to GPU driver struct. + * @param chid [in] Channel Identifier. + * @param caller [in] Caller function name (for reference tracking). * * Same as #nvgpu_channel_get, except that the channel is first retrieved * by chid. @@ -973,14 +973,14 @@ struct nvgpu_channel *nvgpu_channel_from_id__func( /** * @brief Open and initialize a new channel. * - * @param g[in] Pointer to GPU driver struct. - * @param runlist_id[in] Runlist Identifer. + * @param g [in] Pointer to GPU driver struct. + * @param runlist_id [in] Runlist Identifer. * -1 is synonym for #NVGPU_ENGINE_GR. - * @param is_privileged[in] Privileged channel will be able to execute + * @param is_privileged [in] Privileged channel will be able to execute * privileged operations via Host methods on its * pushbuffer. - * @param pid[in] pid of current thread (for tracking). - * @param tid[in] tid of current thread (for tracking). + * @param pid [in] pid of current thread (for tracking). + * @param tid [in] tid of current thread (for tracking). * * Allocates channel from the free list. * Allocates channel instance block. @@ -1003,8 +1003,8 @@ struct nvgpu_channel *nvgpu_channel_open_new(struct gk20a *g, /** * @brief Setup and bind the channel * - * @param ch[in] Channel pointer. - * @param args[in] Setup bind arguments. + * @param ch [in] Channel pointer. + * @param args [in] Setup bind arguments. * * Configures gpfifo and userd for the channel. * Configures channel instance block and commits it to H/W. @@ -1033,8 +1033,8 @@ int nvgpu_channel_setup_bind(struct nvgpu_channel *c, /** * @brief Add/remove channel to/from runlist. * - * @param ch[in] Channel pointer (must be non-NULL). - * @param add[in] True to add a channel, false to remove it. + * @param ch [in] Channel pointer (must be non-NULL). + * @param add [in] True to add a channel, false to remove it. * * When #add is true, adds #ch to runlist. * When #add is false, removes #ch from runlist. @@ -1051,14 +1051,14 @@ int nvgpu_channel_update_runlist(struct nvgpu_channel *c, bool add); /** * @brief Wait until atomic counter is equal to N. * - * @param ch[in] Channel pointer (must be non-NULL). - * @param counter[in] The counter to check. - * @param wait_value[in] The target value for the counter. - * @param c[in] The condition variable to sleep on. This + * @param ch [in] Channel pointer (must be non-NULL). + * @param counter [in] The counter to check. + * @param wait_value [in] The target value for the counter. + * @param c [in] The condition variable to sleep on. This * condition variable is typically signaled * by the thread which updates the counter. - * @param caller_name[in] Function name of caller. - * @param counter_name[in] Counter name. + * @param caller_name [in] Function name of caller. + * @param counter_name [in] Counter name. * * Waits until an atomic counter is equal to N. * It is typically used to check the number of references on a channel. @@ -1075,7 +1075,7 @@ void nvgpu_channel_wait_until_counter_is_N( /** * @brief Free channel's usermode buffers. * - * @param ch[in] Channel pointer (must be non-NULL). + * @param ch [in] Channel pointer (must be non-NULL). * * Frees userspace-managed userd and gpfifo buffers. */ @@ -1099,7 +1099,7 @@ static inline void trace_write_pushbuffers(struct nvgpu_channel *c, u32 count) /** * @brief Mark channel as unserviceable. * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * Once unserviceable, it is not possible to take extra references to * the channel. @@ -1109,7 +1109,7 @@ void nvgpu_channel_set_unserviceable(struct nvgpu_channel *ch); /** * @brief Check if channel is unserviceable * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * @return True if channel is unserviceable, false otherwise. */ @@ -1119,7 +1119,7 @@ bool nvgpu_channel_check_unserviceable(struct nvgpu_channel *ch); /** * @brief Channel userd physical address. * - * @param ch[in] Channel pointer. + * @param ch [in] Channel pointer. * * @return Physical address of channel's userd region. */ @@ -1131,7 +1131,7 @@ static inline u64 nvgpu_channel_userd_addr(struct nvgpu_channel *ch) /** * @brief Channel userd GPU VA. * - * @param c[in] Channel pointer. + * @param c [in] Channel pointer. * * @return GPU virtual address of channel's userd region, or * 0ULL if not mapped. @@ -1146,8 +1146,8 @@ static inline u64 nvgpu_channel_userd_gpu_va(struct nvgpu_channel *c) /** * @brief Allocate channel instance block. * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. * * Instance block is allocated in vidmem if supported by GPU, * sysmem otherwise. @@ -1160,17 +1160,17 @@ int nvgpu_channel_alloc_inst(struct gk20a *g, struct nvgpu_channel *ch); /** * @brief Free channel instance block. * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. */ void nvgpu_channel_free_inst(struct gk20a *g, struct nvgpu_channel *ch); /** * @brief Set error notifier. * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Channel pointer. - * @param error_notifier[in] Error notifier code. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Channel pointer. + * @param error_notifier [in] Error notifier code. * * If an application has installed an error notifier buffer with * #NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER, this function updates @@ -1185,8 +1185,8 @@ void nvgpu_channel_set_error_notifier(struct gk20a *g, struct nvgpu_channel *ch, /** * @brief Get channel from instance block. * - * @param g[in] Pointer to GPU driver struct. - * @param inst_ptr[in] Instance block physical address. + * @param g [in] Pointer to GPU driver struct. + * @param inst_ptr [in] Instance block physical address. * * Search for the channel which instance block physical address is * equal to #inst_ptr. If channel is found, an extra reference is @@ -1200,8 +1200,8 @@ struct nvgpu_channel *nvgpu_channel_refch_from_inst_ptr(struct gk20a *g, /** * @brief Dump debug information for all channels. * - * @param g[in] Pointer to GPU driver struct. - * @param o[in] Debug context (which provides methods to + * @param g [in] Pointer to GPU driver struct. + * @param o [in] Debug context (which provides methods to * output data). * * Dump human-readeable information about active channels. diff --git a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h index e0a2d089b..22918c157 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h @@ -135,7 +135,7 @@ struct nvgpu_engine_status_info { /** * @brief Check if #ctxsw_status is set to switch. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -146,7 +146,7 @@ bool nvgpu_engine_status_is_ctxsw_switch(struct nvgpu_engine_status_info /** * @brief Check if #ctxsw_status is set to load. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -157,7 +157,7 @@ bool nvgpu_engine_status_is_ctxsw_load(struct nvgpu_engine_status_info /** * @brief Check if #ctxsw_status is set to save. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -168,7 +168,7 @@ bool nvgpu_engine_status_is_ctxsw_save(struct nvgpu_engine_status_info /** * @brief Check if #ctxsw_status is set to switch or load or save. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -181,7 +181,7 @@ bool nvgpu_engine_status_is_ctxsw(struct nvgpu_engine_status_info /** * @brief Check if #ctxsw_status is set to invalid. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -192,7 +192,7 @@ bool nvgpu_engine_status_is_ctxsw_invalid(struct nvgpu_engine_status_info /** * @brief - Check if #ctxsw_status is set to valid. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if channel @@ -203,7 +203,7 @@ bool nvgpu_engine_status_is_ctxsw_valid(struct nvgpu_engine_status_info /** * @brief Check if #ctx_id_type is tsg. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if #ctx_id_type @@ -214,7 +214,7 @@ bool nvgpu_engine_status_is_ctx_type_tsg(struct nvgpu_engine_status_info /** * @brief Check if #ctx_next_id_type is tsg. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. * * @return Interprets #engine_status and returns true if @@ -226,11 +226,11 @@ bool nvgpu_engine_status_is_next_ctx_type_tsg(struct nvgpu_engine_status_info /** * @brief Get ctx_id and ctx_id_type info. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. - * @param ctx_id[out] Pointer that is updated with #ctx_id as set in + * @param ctx_id [out] Pointer that is updated with #ctx_id as set in * input param #engine_status. - * @param ctx_type[out] Pointer that is updated with #ctx_id_type as set + * @param ctx_type [out] Pointer that is updated with #ctx_id_type as set * in input param #engine_status. * * @return Interprets #engine_status and updates input params #ctx_id @@ -241,11 +241,11 @@ void nvgpu_engine_status_get_ctx_id_type(struct nvgpu_engine_status_info /** * @brief Get next_ctx_id and next_ctx_id_type info. * - * @param engine_status[in] Pointer to struct containing engine_status h/w + * @param engine_status [in] Pointer to struct containing engine_status h/w * reg/field value. - * @param ctx_next_id[out] Pointer that is updated with #ctx_next_id as set + * @param ctx_next_id [out] Pointer that is updated with #ctx_next_id as set * in input param #engine_status. - * @param ctx_next_type[out] Pointer that is updated with #ctx_next_id_type + * @param ctx_next_type [out] Pointer that is updated with #ctx_next_id_type * as set in input param #engine_status. * * @return Interprets #engine_status and updates input params diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index e398ece15..03d4962be 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -99,8 +99,8 @@ struct nvgpu_engine_info { * @brief Get s/w defined engine enum type for engine enum type defined by h/w. * See top.h for engine enum types defined by h/w. * - * @param g[in] The GPU driver struct. - * @param engine_type[in] Engine enum type defined by h/w. + * @param g [in] The GPU driver struct. + * @param engine_type [in] Engine enum type defined by h/w. * * This is used to map engine enum type defined by h/w to engine enum type * defined by s/w. @@ -116,8 +116,8 @@ enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g, /** * @brief Get pointer to #nvgpu_engine_info for the h/w engine id. * - * @param g[in] The GPU driver struct. - * @param engine_id[in] Active (h/w) Engine id. + * @param g [in] The GPU driver struct. + * @param engine_id [in] Active (h/w) Engine id. * * If #engine_id is one of the supported h/w engine ids, get pointer to * #nvgpu_engine_info from an array of structures that is indexed by h/w @@ -136,11 +136,11 @@ struct nvgpu_engine_info *nvgpu_engine_get_active_eng_info( * @brief Get instance count and h/w engine id/s for s/w defined engine * enum type. See #nvgpu_fifo_engine for s/w defined engine enum types. * - * @param g[in] The GPU driver struct. - * @param engine_ids[in,out] Pointer to memory area to store h/w engine ids. - * @param engine_id_sz[in] Number of h/w engine ids to be stored in + * @param g [in] The GPU driver struct. + * @param engine_ids [in,out] Pointer to memory area to store h/w engine ids. + * @param engine_id_sz [in] Number of h/w engine ids to be stored in * memory area pointed by #engine_ids. - * @param engine_enum[in] Engine enum types defined by #nvgpu_fifo_engine. + * @param engine_enum [in] Engine enum types defined by #nvgpu_fifo_engine. * * - Check validity of input parameters. * - Get #nvgpu_engine_info for each of #nvgpu_fifo.num_engines. @@ -159,8 +159,8 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, /** * @brief Check if engine id is one of the supported h/w engine ids. * - * @param g[in] The GPU driver struct. - * @param engine_id[in] Engine id. + * @param g [in] The GPU driver struct. + * @param engine_id [in] Engine id. * * Check if #engine_id is one of the supported active engine ids. * @@ -174,7 +174,7 @@ bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id); * @brief Get instance count and first available h/w engine id for * #NVGPU_ENGINE_GR engine enum type. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Call #nvgpu_engine_get_ids to get first available #NVGPU_ENGINE_GR * engine enum type. @@ -187,7 +187,7 @@ u32 nvgpu_engine_get_gr_id(struct gk20a *g); /** * @brief Get intr mask for the engines supported by the chip. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * For each of #nvgpu_fifo.num_engines, get pointer to * #nvgpu_engine_info. Use this to get #nvgpu_engine_info.intr_mask. @@ -206,8 +206,8 @@ u32 nvgpu_engine_interrupt_mask(struct gk20a *g); /** * @brief Get intr mask for the h/w engine id. * - * @param g[in] The GPU driver struct. - * @param act_eng_id[in] H/w Engine id. + * @param g [in] The GPU driver struct. + * @param act_eng_id [in] H/w Engine id. * * Get pointer to #nvgpu_engine_info for the #act_eng_id. Use this to * get intr mask for the #act_eng_id. @@ -220,7 +220,7 @@ u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id); /** * @brief Get engine reset mask for CE engines. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * For each #nvgpu_fifo.num_engines, get pointer to #nvgpu_engine_info. * Use this pointer to check if engine enum type matches with @@ -237,7 +237,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g); /** * @brief Allocate and initialize s/w context for engine related info. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * - Get max number of engines supported on the chip from h/w config register. * - Allocate kernel memory area for storing engine info for max number of @@ -263,7 +263,7 @@ int nvgpu_engine_setup_sw(struct gk20a *g); /** * @brief Clean up s/w context for engine related info. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * - Free up kernel memory area that is used for storing engine info read * from device info h/w registers. @@ -295,7 +295,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id); * @brief Get runlist id for the last available #NVGPU_ENGINE_ASYNC_CE * engine enum type. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * - Call #nvgpu_engine_get_gr_runlist_id to get runlist id for the first * available #NVGPU_ENGINE_GR engine type. @@ -318,7 +318,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g); * @brief Get runlist id for the first available #NVGPU_ENGINE_GR engine enum * type. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * - Get h/w engine id for the first available #NVGPU_ENGINE_GR engine enum * type. @@ -335,8 +335,8 @@ u32 nvgpu_engine_get_gr_runlist_id(struct gk20a *g); * @brief Check if runlist id corresponds to runlist id of one of the * engine ids supported by h/w. * - * @param g[in] The GPU driver struct. - * @param runlist_id[in] Runlist id. + * @param g [in] The GPU driver struct. + * @param runlist_id [in] Runlist id. * * Check if #runlist_id corresponds to runlist id of one of the engine * ids supported by h/w by checking #nvgpu_engine_info for each of @@ -351,8 +351,8 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id); /** * @brief Get mmu fault id for the engine id. * - * @param g[in] The GPU driver struct. - * @param engine_id[in] Engine id. + * @param g [in] The GPU driver struct. + * @param engine_id [in] Engine id. * * Get pointer to #nvgpu_engine_info for the #engine_id. Use this pointer to * get mmu fault id for the #engine_id. @@ -364,8 +364,8 @@ u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id); /** * @brief Get engine id from mmu fault id. * - * @param g[in] The GPU driver struct. - * @param fault_id[in] Mmu fault id. + * @param g [in] The GPU driver struct. + * @param fault_id [in] Mmu fault id. * * Check if #fault_id corresponds to fault id of one of the active engine * ids supported by h/w by checking #nvgpu_engine_info for each of @@ -386,7 +386,7 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg); /** * @brief Read device info h/w registers to get engine info. * - * @param f[in] Pointer to #nvgpu_fifo struct. + * @param f [in] Pointer to #nvgpu_fifo struct. * * - Get device info related info for h/w engine enum type, * #NVGPU_ENGINE_GRAPHICS. @@ -436,9 +436,9 @@ bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id, /** * @brief Get veid from mmu fault id. * - * @param g[in] The GPU driver struct. - * @param mmu_fault_id[in] Mmu fault id. - * @param gr_eng_fault_id[in] GR engine's mmu fault id. + * @param g [in] The GPU driver struct. + * @param mmu_fault_id [in] Mmu fault id. + * @param gr_eng_fault_id [in] GR engine's mmu fault id. * * Get valid veid by subtracting #gr_eng_fault_id from #mmu_fault_id, * if #mmu_fault_id is greater than or equal to #gr_eng_fault_id and less @@ -452,9 +452,9 @@ u32 nvgpu_engine_mmu_fault_id_to_veid(struct gk20a *g, u32 mmu_fault_id, /** * @brief Get h/w engine id and veid from mmu fault id. * - * @param g[in] The GPU driver struct. - * @param mmu_fault_id[in] Mmu fault id. - * @param veid[in,out] Pointer to store veid. + * @param g [in] The GPU driver struct. + * @param mmu_fault_id [in] Mmu fault id. + * @param veid [in,out] Pointer to store veid. * * Get valid h/w engine id for given #mmu_fault_id. Also get veid if engine * enum for h/w engine id is of type #NVGPU_ENGINE_GR. @@ -468,11 +468,11 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, /** * @brief Get engine id, veid and pbdma id from mmu fault id. * - * @param g[in] The GPU driver struct. - * @param mmu_fault_id[in] Mmu fault id. - * @param act_eng_id[in,out] Pointer to store active engine id. - * @param veid[in,out] Pointer to store veid. - * @param pbdma_id[in,out] Pointer to store pbdma id. + * @param g [in] The GPU driver struct. + * @param mmu_fault_id [in] Mmu fault id. + * @param act_eng_id [in,out] Pointer to store active engine id. + * @param veid [in,out] Pointer to store veid. + * @param pbdma_id [in,out] Pointer to store pbdma id. * * Calls function to get h/w engine id and veid for given #mmu_fault_id. * If h/w (active) engine id is not #INVAL_ID, call function to get pbdma id for diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h index deae4727d..38e2c0cec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h @@ -401,7 +401,7 @@ struct nvgpu_fifo { /** * @brief Initialize FIFO software context. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Calls function to do setup_sw. Refer #nvgpu_fifo_setup_sw. * If setup_sw was successful, call function to do setup_hw. This is to take @@ -415,7 +415,7 @@ int nvgpu_fifo_init_support(struct gk20a *g); /** * @brief Initialize FIFO software context and mark it ready to be used. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Return if #nvgpu_fifo.sw_ready is set to true i.e. s/w set up is already * done. @@ -430,7 +430,7 @@ int nvgpu_fifo_setup_sw(struct gk20a *g); /** * @brief Initialize FIFO software context. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Init mutexes needed by FIFO module. Refer #nvgpu_fifo struct. * Do #nvgpu_channel_setup_sw. @@ -450,7 +450,7 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g); /** * @brief Clean up FIFO software context. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Deinit Channel worker thread. * Calls #nvgpu_fifo_cleanup_sw_common. @@ -460,7 +460,7 @@ void nvgpu_fifo_cleanup_sw(struct gk20a *g); /** * @brief Clean up FIFO software context and related resources. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Do userd.cleanup_sw. * Do #nvgpu_channel_cleanup_sw. @@ -475,7 +475,7 @@ void nvgpu_fifo_cleanup_sw_common(struct gk20a *g); /** * @brief Decode PBDMA channel status and Engine status read from h/w register. * - * @param index[in] Status value used to index into the constant array of + * @param index [in] Status value used to index into the constant array of * constant characters. * * Decode PBDMA channel status and Engine status value read from h/w @@ -486,7 +486,7 @@ const char *nvgpu_fifo_decode_pbdma_ch_eng_status(u32 index); /** * @brief Suspend FIFO support while preparing GPU for poweroff. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Suspending FIFO will disable BAR1 snooping (if supported by h/w) and also * FIFO interrupts. @@ -497,7 +497,7 @@ int nvgpu_fifo_suspend(struct gk20a *g); /** * @brief Emergency quiescing of FIFO. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Gracefully put FIFO into a non-functioning state to ensure that no corrupted * work is completed because of the fault. This is because the freedom diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h index 54e4305f5..42c2c846f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h @@ -37,7 +37,7 @@ struct nvgpu_gr_config; /** * @brief Initialize GR engine configuration information. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function reads GR engine configuration from GPU h/w and stores * it in #nvgpu_gr_config struct. @@ -60,8 +60,8 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g); /** * @brief Deinitialize GR engine configuration. * - * @param g[in] Pointer to GPU driver struct. - * @param config[in] Pointer to GR configuration struct. + * @param g [in] Pointer to GPU driver struct. + * @param config [in] Pointer to GR configuration struct. * * This function will free memory allocated to hold GR engine * configuration information in #nvgpu_gr_config_init(). @@ -71,7 +71,7 @@ void nvgpu_gr_config_deinit(struct gk20a *g, struct nvgpu_gr_config *config); /** * @brief Get max GPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns maximum number of GPCs available in a GPU chip * family. @@ -83,7 +83,7 @@ u32 nvgpu_gr_config_get_max_gpc_count(struct nvgpu_gr_config *config); /** * @brief Get max TPC per GPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns maximum number of TPCs available per GPC in a * GPU chip family. @@ -95,7 +95,7 @@ u32 nvgpu_gr_config_get_max_tpc_per_gpc_count(struct nvgpu_gr_config *config); /** * @brief Get max TPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns maximum number of TPCs available in a GPU chip * family. @@ -107,7 +107,7 @@ u32 nvgpu_gr_config_get_max_tpc_count(struct nvgpu_gr_config *config); /** * @brief Get available GPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of available GPCs in GR engine. * Note that other GPCs are floorswept or not available. @@ -119,7 +119,7 @@ u32 nvgpu_gr_config_get_gpc_count(struct nvgpu_gr_config *config); /** * @brief Get available TPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of available TPCs in GR engine. * Note that other TPCs are floorswept or not available. @@ -131,7 +131,7 @@ u32 nvgpu_gr_config_get_tpc_count(struct nvgpu_gr_config *config); /** * @brief Get available PPC count. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of available PPCs in GR engine. * @@ -142,7 +142,7 @@ u32 nvgpu_gr_config_get_ppc_count(struct nvgpu_gr_config *config); /** * @brief Get PES count per GPC. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of PES units per GPC. * @@ -153,7 +153,7 @@ u32 nvgpu_gr_config_get_pe_count_per_gpc(struct nvgpu_gr_config *config); /** * @brief Get SM count per TPC. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of SMs per TPC. * @@ -164,8 +164,8 @@ u32 nvgpu_gr_config_get_sm_count_per_tpc(struct nvgpu_gr_config *config); /** * @brief Get PPC count for given GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. * * This function returns number of PPCs for given GPC index. * @@ -177,7 +177,7 @@ u32 nvgpu_gr_config_get_gpc_ppc_count(struct nvgpu_gr_config *config, /** * @brief Get base address of array that stores number of TPCs in GPC. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * Number of TPCs per GPC are stored in an array indexed by GPC index. * This function returns base address of this array. @@ -189,8 +189,8 @@ u32 *nvgpu_gr_config_get_gpc_tpc_count_base(struct nvgpu_gr_config *config); /** * @brief Get TPC count for given GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. * * This function returns number of TPCs for given GPC index. * @@ -202,9 +202,9 @@ u32 nvgpu_gr_config_get_gpc_tpc_count(struct nvgpu_gr_config *config, /** * @brief Get TPC count for given PES/GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. - * @param pes_index[in] Index of PES. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. + * @param pes_index [in] Index of PES. * * A GPC includes multiple TPC and PES units. A PES unit has multiple * TPC units connected to it within same GPC. @@ -219,7 +219,7 @@ u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config, /** * @brief Get base address of array that stores mask of TPCs in GPC. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * Masks of TPCs per GPC are stored in an array indexed by GPC index. * This function returns base address of this array. @@ -231,8 +231,8 @@ u32 *nvgpu_gr_config_get_gpc_tpc_mask_base(struct nvgpu_gr_config *config); /** * @brief Get TPC mask for given GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. * * This function returns mask of TPCs for given GPC index. * Each set bit indicates TPC with that index is available, otherwise @@ -246,9 +246,9 @@ u32 nvgpu_gr_config_get_gpc_tpc_mask(struct nvgpu_gr_config *config, /** * @brief Set TPC mask for given GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. - * @param val[in] Mask value to be set. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. + * @param val [in] Mask value to be set. * * This function sets the TPC mask in #nvgpu_gr_config struct * for given GPC index. @@ -259,8 +259,8 @@ void nvgpu_gr_config_set_gpc_tpc_mask(struct nvgpu_gr_config *config, /** * @brief Get TPC skip mask for given GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. * * This function returns skip mask of TPCs for given GPC index. * This mask will be used to skip certain TPC during load balancing @@ -274,9 +274,9 @@ u32 nvgpu_gr_config_get_gpc_skip_mask(struct nvgpu_gr_config *config, /** * @brief Get TPC mask for given PES/GPC. * - * @param config[in] Pointer to GR configuration struct. - * @param gpc_index[in] Index of GPC. - * @param pes_index[in] Index of PES. + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Index of GPC. + * @param pes_index [in] Index of PES. * * A GPC includes multiple TPC and PES units. A PES unit has multiple * TPC units connected to it within same GPC. @@ -291,7 +291,7 @@ u32 nvgpu_gr_config_get_pes_tpc_mask(struct nvgpu_gr_config *config, /** * @brief Get mask of GPCs. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns mask of GPCs in GR engine. Each set bit indicates * GPC with that index is available, otherwise the GPC is considered @@ -304,7 +304,7 @@ u32 nvgpu_gr_config_get_gpc_mask(struct nvgpu_gr_config *config); /** * @brief Get number of SMs. * - * @param config[in] Pointer to GR configuration struct. + * @param config [in] Pointer to GR configuration struct. * * This function returns number of SMs in GR engine. * @@ -315,8 +315,8 @@ u32 nvgpu_gr_config_get_no_of_sm(struct nvgpu_gr_config *config); /** * @brief Set number of SMs. * - * @param config[in] Pointer to GR configuration struct. - * @param no_of_sm[in] SM count to be set. + * @param config [in] Pointer to GR configuration struct. + * @param no_of_sm [in] SM count to be set. * * This function sets number of SMs in #nvgpu_gr_config struct. */ @@ -325,8 +325,8 @@ void nvgpu_gr_config_set_no_of_sm(struct nvgpu_gr_config *config, u32 no_of_sm); /** * @brief Get information of given SM. * - * @param config[in] Pointer to GR configuration struct. - * @param sm_id[in] SM index. + * @param config [in] Pointer to GR configuration struct. + * @param sm_id [in] SM index. * * common.gr unit stores information of each SM into an array of struct * #nvgpu_sm_info. This information includes GPC/TPC indexes for @@ -343,7 +343,7 @@ struct nvgpu_sm_info *nvgpu_gr_config_get_sm_info(struct nvgpu_gr_config *config /** * @brief Get GPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. + * @param sm_info [in] Pointer to SM information struct. * * This function returns GPC index of SM from given #nvgpu_sm_info struct. * @@ -354,8 +354,8 @@ u32 nvgpu_gr_config_get_sm_info_gpc_index(struct nvgpu_sm_info *sm_info); /** * @brief Set GPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. - * @param gpc_index[in] GPC index to be set. + * @param sm_info [in] Pointer to SM information struct. + * @param gpc_index [in] GPC index to be set. * * This function sets GPC index of SM into given #nvgpu_sm_info struct. */ @@ -365,7 +365,7 @@ void nvgpu_gr_config_set_sm_info_gpc_index(struct nvgpu_sm_info *sm_info, /** * @brief Get TPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. + * @param sm_info [in] Pointer to SM information struct. * * This function returns TPC index of SM from given #nvgpu_sm_info struct. * @@ -376,8 +376,8 @@ u32 nvgpu_gr_config_get_sm_info_tpc_index(struct nvgpu_sm_info *sm_info); /** * @brief Set TPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. - * @param tpc_index[in] TPC index to be set. + * @param sm_info [in] Pointer to SM information struct. + * @param tpc_index [in] TPC index to be set. * * This function sets TPC index of SM into given #nvgpu_sm_info struct. */ @@ -387,7 +387,7 @@ void nvgpu_gr_config_set_sm_info_tpc_index(struct nvgpu_sm_info *sm_info, /** * @brief Get global TPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. + * @param sm_info [in] Pointer to SM information struct. * * This function returns global TPC index of SM from given #nvgpu_sm_info * struct. Global index is assigned to TPC considering all TPCs in all GPCs. @@ -399,8 +399,8 @@ u32 nvgpu_gr_config_get_sm_info_global_tpc_index(struct nvgpu_sm_info *sm_info); /** * @brief Set global TPC index of SM. * - * @param sm_info[in] Pointer to SM information struct. - * @param global_tpc_index[in] Global TPC index to be set. + * @param sm_info [in] Pointer to SM information struct. + * @param global_tpc_index [in] Global TPC index to be set. * * This function sets global TPC index of SM into given #nvgpu_sm_info struct. * Global index is assigned to TPC considering all TPCs in all GPCs. @@ -411,7 +411,7 @@ void nvgpu_gr_config_set_sm_info_global_tpc_index(struct nvgpu_sm_info *sm_info, /** * @brief Get index of SM within TPC. * - * @param sm_info[in] Pointer to SM information struct. + * @param sm_info [in] Pointer to SM information struct. * * This function returns index of SM within TPC from given #nvgpu_sm_info * struct. e.g. GV11B GPU has 2 SMs in a TPC. So this function will return @@ -424,8 +424,8 @@ u32 nvgpu_gr_config_get_sm_info_sm_index(struct nvgpu_sm_info *sm_info); /** * @brief Set index of SM within TPC. * - * @param sm_info[in] Pointer to SM information struct. - * @param sm_index[in] SM index. + * @param sm_info [in] Pointer to SM information struct. + * @param sm_index [in] SM index. * * This function sets index of SM within TPC into given #nvgpu_sm_info * struct. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h index c7261dd29..11d194e8f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h @@ -131,7 +131,7 @@ struct zcull_ctx_desc; /** * @brief Initialize GR context descriptor structure. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for #nvgpu_gr_ctx_desc structure. * @@ -143,8 +143,8 @@ struct nvgpu_gr_ctx_desc *nvgpu_gr_ctx_desc_alloc(struct gk20a *g); /** * @brief Free GR context descriptor structure. * - * @param g[in] Pointer to GPU driver struct. - * @param desc[in] Pointer to context descriptor struct. + * @param g [in] Pointer to GPU driver struct. + * @param desc [in] Pointer to context descriptor struct. * * This function will free memory allocated for #nvgpu_gr_ctx_desc structure. */ @@ -154,9 +154,9 @@ void nvgpu_gr_ctx_desc_free(struct gk20a *g, /** * @brief Set size of GR context buffer with given index. * - * @param desc[in] Pointer to context descriptor struct. - * @param index[in] Index of GR context buffer. - * @param size[in] Size of buffer to be set. + * @param desc [in] Pointer to context descriptor struct. + * @param index [in] Index of GR context buffer. + * @param size [in] Size of buffer to be set. * * This function sets size of GR context buffer with given buffer * index. @@ -167,10 +167,10 @@ void nvgpu_gr_ctx_set_size(struct nvgpu_gr_ctx_desc *gr_ctx_desc, /** * @brief Allocate graphics context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param gr_ctx_desc[in] Pointer to context descriptor struct. - * @param vm[in] Pointer to virtual memory. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param gr_ctx_desc [in] Pointer to context descriptor struct. + * @param vm [in] Pointer to virtual memory. * * This function allocates memory for graphics context buffer and also * maps it to given virtual memory. @@ -188,10 +188,10 @@ int nvgpu_gr_ctx_alloc(struct gk20a *g, /** * @brief Free graphics context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param global_ctx_buffer[in] Pointer to global context descriptor struct. - * @param vm[in] Pointer to virtual memory. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param global_ctx_buffer [in]Pointer to global context descriptor struct. + * @param vm [in] Pointer to virtual memory. * * This function will free memory allocated for graphics context buffer, * patch context buffer, and all the ctxsw buffers. @@ -204,10 +204,10 @@ void nvgpu_gr_ctx_free(struct gk20a *g, /** * @brief Allocate patch context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param gr_ctx_desc[in] Pointer to context descriptor struct. - * @param vm[in] Pointer to virtual memory. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param gr_ctx_desc [in] Pointer to context descriptor struct. + * @param vm [in] Pointer to virtual memory. * * This function allocates memory for patch context buffer and also * maps it to given virtual memory. @@ -223,9 +223,9 @@ int nvgpu_gr_ctx_alloc_patch_ctx(struct gk20a *g, /** * @brief Free patch context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param vm[in] Pointer to virtual memory. - * @param gr_ctx[in] Pointer to graphics context struct. + * @param g [in] Pointer to GPU driver struct. + * @param vm [in] Pointer to virtual memory. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function will free memory allocated for patch context buffer. */ @@ -235,11 +235,11 @@ void nvgpu_gr_ctx_free_patch_ctx(struct gk20a *g, struct vm_gk20a *vm, /** * @brief Map global context buffers. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param global_ctx_buffer[in] Pointer to global context descriptor struct. - * @param vm[in] Pointer to virtual memory. - * @param vpr[in] Boolean flag to use buffers in VPR. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param global_ctx_buffer [in]Pointer to global context descriptor struct. + * @param vm [in] Pointer to virtual memory. + * @param vpr [in] Boolean flag to use buffers in VPR. * * This function maps all global context buffers into given * virtual memory and stores each virtual address into given @@ -256,8 +256,8 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, /** * @brief Get global context buffer virtual address. * - * @param gr_ctx[in] Pointer to graphics context struct. - * @param index[in] Index of global context buffer. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param index [in] Index of global context buffer. * * This function returns virtual address of global context buffer * with given index stored in #nvgpu_gr_ctx struct. @@ -270,7 +270,7 @@ u64 nvgpu_gr_ctx_get_global_ctx_va(struct nvgpu_gr_ctx *gr_ctx, /** * @brief Get pointer of patch context buffer memory struct. * - * @param gr_ctx[in] Pointer to graphics context struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function returns #nvgpu_mem pointer of patch context buffer stored * in #nvgpu_gr_ctx struct. @@ -282,8 +282,8 @@ struct nvgpu_mem *nvgpu_gr_ctx_get_patch_ctx_mem(struct nvgpu_gr_ctx *gr_ctx); /** * @brief Set data count in patch context buffer. * - * @param gr_ctx[in] Pointer to graphics context struct. - * @param data_count[in] Value to be set. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param data_count [in] Value to be set. * * This function sets data count of patch context buffer. Data count * indicates how many entries have been written into patch context. @@ -294,7 +294,7 @@ void nvgpu_gr_ctx_set_patch_ctx_data_count(struct nvgpu_gr_ctx *gr_ctx, /** * @brief Get pointer of graphics context buffer memory struct. * - * @param gr_ctx[in] Pointer to graphics context struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function returns #nvgpu_mem pointer of graphics context buffer. * @@ -305,10 +305,10 @@ struct nvgpu_mem *nvgpu_gr_ctx_get_ctx_mem(struct nvgpu_gr_ctx *gr_ctx); /** * @brief Load local golden image into given graphics context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param local_golden_image[in] Pointer to local golden image struct. - * @param cde[in] Boolean flag to enable/disable CDE. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param local_golden_image [in] Pointer to local golden image struct. + * @param cde [in] Boolean flag to enable/disable CDE. * * This function loads local golden image copy into given new graphics * context buffer. @@ -327,9 +327,9 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, /** * @brief Prepare patch context buffer for writes. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param update_patch_count[in] Boolean flag to update data count + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param update_patch_count [in] Boolean flag to update data count * in patch context. * * This function will prepare patch context buffer for writes. This @@ -343,9 +343,9 @@ void nvgpu_gr_ctx_patch_write_begin(struct gk20a *g, /** * @brief Finish patch context buffer writes. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param update_patch_count[in] Boolean flag to update data count + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param update_patch_count [in] Boolean flag to update data count * in patch context. * * This function will write final data count into patch context image @@ -359,11 +359,11 @@ void nvgpu_gr_ctx_patch_write_end(struct gk20a *g, /** * @brief Edit the context state. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param addr[in] Address entry to be added. - * @param data[in] Data entry to be added. - * @param patch[in] Boolean flag. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param addr [in] Address entry to be added. + * @param data [in] Data entry to be added. + * @param patch [in] Boolean flag. * * This function will write given addr and data entries into patch * context buffer if boolean flag patch is set. In this case, the @@ -383,8 +383,8 @@ void nvgpu_gr_ctx_patch_write(struct gk20a *g, /** * @brief Set given compute preemption mode in graphics context struct. * - * @param gr_ctx[in] Pointer to graphics context struct. - * @param compute_preempt_mode[in] Compute preemption mode to be set. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param compute_preempt_mode [in] Compute preemption mode to be set. * * This function will set given compute preemption mode into #nvgpu_gr_ctx * structure. @@ -395,7 +395,7 @@ void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, /** * @brief Get compute preemption mode stored in graphics context struct. * - * @param gr_ctx[in] Pointer to graphics context struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function returns compute preemption mode stored in #nvgpu_gr_ctx * struct. @@ -407,7 +407,7 @@ u32 nvgpu_gr_ctx_get_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx); /** * @brief Check if given preemption modes are valid. * - * @param gr_ctx[in] Pointer to graphics context struct. + * @param gr_ctx [in] Pointer to graphics context struct. * @param graphics_preempt_mode Requested graphics preemption mode. * @param compute_preempt_mode Requested compute preemption mode. * @@ -431,8 +431,8 @@ bool nvgpu_gr_ctx_check_valid_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, /** * @brief Write preemption modes in graphics context image. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function writes graphics/compute preemption modes into graphics * context image. Preemption mode values are taken from #nvgpu_gr_ctx @@ -444,7 +444,7 @@ void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g, /** * @brief Initialize GR context structure. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for #nvgpu_gr_ctx structure. * @@ -456,8 +456,8 @@ struct nvgpu_gr_ctx *nvgpu_alloc_gr_ctx_struct(struct gk20a *g); /** * @brief Free GR context structure. * - * @param g[in] Pointer to GPU driver struct. - * @param gr_ctx[in] Pointer to graphics context struct. + * @param g [in] Pointer to GPU driver struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function will free memory allocated for #nvgpu_gr_ctx structure. */ @@ -466,8 +466,8 @@ void nvgpu_free_gr_ctx_struct(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); /** * @brief Set TSG id in graphics context structure. * - * @param gr_ctx[in] Pointer to graphics context struct. - * @param tsgid[in] TSG identifier. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param tsgid [in] TSG identifier. * * This function will set given TSG identifier into #nvgpu_gr_ctx * structure. @@ -477,7 +477,7 @@ void nvgpu_gr_ctx_set_tsgid(struct nvgpu_gr_ctx *gr_ctx, u32 tsgid); /** * @brief Get TSG id stored in graphics context structure. * - * @param gr_ctx[in] Pointer to graphics context struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function will return TSG identifier stored in #nvgpu_gr_ctx * structure. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h index 4e07884ea..6e643d787 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h @@ -34,8 +34,8 @@ struct nvgpu_gr_config; /** * @brief Initialize GR engine h/w state post-floorsweeping. * - * @param g[in] Pointer to GPU driver struct. - * @param config[in] Pointer to GR config struct. + * @param g [in] Pointer to GPU driver struct. + * @param config [in] Pointer to GR config struct. * * This function initializes GR engine h/w state after considering * floorsweeping. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h index b63030a5e..eb2e8e91a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/global_ctx.h @@ -88,7 +88,7 @@ typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g, /** * @brief Initialize global context descriptor structure. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for #nvgpu_gr_global_ctx_buffer_desc * structure. @@ -102,8 +102,8 @@ struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_global_ctx_desc_alloc( /** * @brief Free global context descriptor structure. * - * @param g[in] Pointer to GPU driver struct. - * @param desc[in] Pointer to global context descriptor struct. + * @param g [in] Pointer to GPU driver struct. + * @param desc [in] Pointer to global context descriptor struct. * * This function will free memory allocated for * #nvgpu_gr_global_ctx_buffer_desc structure. @@ -114,9 +114,9 @@ void nvgpu_gr_global_ctx_desc_free(struct gk20a *g, /** * @brief Set size of global context buffer with given index. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. - * @param size[in] Size of buffer to be set. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. + * @param size [in] Size of buffer to be set. * * This function sets size of global context buffer with given buffer * index. @@ -127,8 +127,8 @@ void nvgpu_gr_global_ctx_set_size(struct nvgpu_gr_global_ctx_buffer_desc *desc, /** * @brief Get size of global context buffer with given index. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. * * This function will return size of global context buffer with given buffer * index. @@ -141,8 +141,8 @@ size_t nvgpu_gr_global_ctx_get_size(struct nvgpu_gr_global_ctx_buffer_desc *desc /** * @brief Allocate all global context buffers. * - * @param g[in] Pointer to GPU driver struct. - * @param desc[in] Pointer to global context descriptor struct. + * @param g [in] Pointer to GPU driver struct. + * @param desc [in] Pointer to global context descriptor struct. * * This function allocates memory for all global context buffers. * @@ -161,8 +161,8 @@ int nvgpu_gr_global_ctx_buffer_alloc(struct gk20a *g, /** * @brief Free all global context buffers. * - * @param g[in] Pointer to GPU driver struct. - * @param desc[in] Pointer to global context descriptor struct. + * @param g [in] Pointer to GPU driver struct. + * @param desc [in] Pointer to global context descriptor struct. * * This function will free memory allocated for all global context * buffers. @@ -173,11 +173,11 @@ void nvgpu_gr_global_ctx_buffer_free(struct gk20a *g, /** * @brief Map given global context buffer. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. - * @param vm[in] Pointer to virtual memory. - * @param flags[in] Flags used to specify mapping attributes. - * @param priv[in] Boolean flag to allocate privileged PTE. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. + * @param vm [in] Pointer to virtual memory. + * @param flags [in] Flags used to specify mapping attributes. + * @param priv [in] Boolean flag to allocate privileged PTE. * * This function maps given global contex buffer with index #index into * given virtual memory. @@ -192,10 +192,10 @@ u64 nvgpu_gr_global_ctx_buffer_map(struct nvgpu_gr_global_ctx_buffer_desc *desc, /** * @brief Unmap given global context buffer. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. - * @param vm[in] Pointer to virtual memory. - * @param gpu_va[in] GPU virtual address to unmap. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. + * @param vm [in] Pointer to virtual memory. + * @param gpu_va [in] GPU virtual address to unmap. * * This function unmaps given global contex buffer with index #index from * given virtual memory. @@ -208,8 +208,8 @@ void nvgpu_gr_global_ctx_buffer_unmap( /** * @brief Get pointer of global context buffer memory struct. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. * * This function returns #nvgpu_mem pointer of global context buffer * stored in #nvgpu_gr_global_ctx_buffer_desc struct. @@ -223,8 +223,8 @@ struct nvgpu_mem *nvgpu_gr_global_ctx_buffer_get_mem( /** * @brief Check if given global context buffer is ready. * - * @param desc[in] Pointer to global context descriptor struct. - * @param index[in] Index of global context buffer. + * @param desc [in] Pointer to global context descriptor struct. + * @param index [in] Index of global context buffer. * * This function checks if memory has been allocated for requested * global context buffer with index #index. @@ -239,9 +239,9 @@ bool nvgpu_gr_global_ctx_buffer_ready( /** * @brief Initialize local golden context image. * - * @param g[in] Pointer to GPU driver struct. - * @param source_mem[in] Pointer to source memory. - * @param size[in] Size of local golden context image. + * @param g [in] Pointer to GPU driver struct. + * @param source_mem [in] Pointer to source memory. + * @param size [in] Size of local golden context image. * * This function allocates memory to store local golden context image * and also for #nvgpu_gr_global_ctx_local_golden_image structure. @@ -263,9 +263,9 @@ nvgpu_gr_global_ctx_init_local_golden_image(struct gk20a *g, /** * @brief Load local golden context image into target memory. * - * @param g[in] Pointer to GPU driver struct. - * @param local_golden_image[in] Pointer to local golden context image struct. - * @param target_mem[in] Pointer to target memory. + * @param g [in] Pointer to GPU driver struct. + * @param local_golden_image [in] Pointer to local golden context image struct. + * @param target_mem [in] Pointer to target memory. * * This function copies contents of local golden context image to * given target memory. Target memory is usually a new graphics context @@ -278,7 +278,7 @@ void nvgpu_gr_global_ctx_load_local_golden_image(struct gk20a *g, /** * @brief Deinit local golden context image. * - * @param local_golden_image[in] Pointer to local golden context image struct. + * @param local_golden_image [in] Pointer to local golden context image struct. * * This function will free memory allocated for local golden context * image and for #nvgpu_gr_global_ctx_local_golden_image struct. @@ -290,11 +290,11 @@ void nvgpu_gr_global_ctx_deinit_local_golden_image(struct gk20a *g, /** * @brief Compare two local golden images. * - * @param g[in] Pointer to GPU driver struct. - * @param is_sysmem[in] Boolean flag to indicate images are in sysmem. + * @param g [in] Pointer to GPU driver struct. + * @param is_sysmem [in] Boolean flag to indicate images are in sysmem. * @param local_golden_image1[in] Pointer to first local golden context image struct. * @param local_golden_image2[in] Pointer to second local golden context image struct. - * @param size[in] Size of local golden context image. + * @param size [in] Size of local golden context image. * * This function compares contents of two local golden images and * returns true only if they match. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h index fd03068c9..7c3a82756 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h @@ -121,7 +121,7 @@ struct nvgpu_gr_config; /** * @brief Allocate memory for GR struct. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for GR struct (i.e. struct nvgpu_gr). * @@ -133,7 +133,7 @@ int nvgpu_gr_alloc(struct gk20a *g); /** * @brief Free GR struct. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function ensures that memory allocated for GR struct is released * during deinitialization. @@ -143,7 +143,7 @@ void nvgpu_gr_free(struct gk20a *g); /** * @brief Initialize GR struct fields * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Calling this function ensures that various GR struct fields are * initialized before they are referenced by other units or before @@ -154,7 +154,7 @@ void nvgpu_gr_init(struct gk20a *g); /** * @brief Initialize the s/w required to enable h/w. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function executes only a subset of s/w initialization sequence * that is required to enable GR engine h/w in #nvgpu_gr_enable_hw(). @@ -174,7 +174,7 @@ int nvgpu_gr_prepare_sw(struct gk20a *g); /** * @brief Enable GR engine h/w. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function enables GR engine h/w. This includes: * - Resetting GR engine in MC. @@ -195,7 +195,7 @@ int nvgpu_gr_enable_hw(struct gk20a *g); /** * @brief Initialize GR engine support. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function initializes all the GR engine support and * functionality. This includes: @@ -224,7 +224,7 @@ int nvgpu_gr_init_support(struct gk20a *g); /** * @brief Wait for GR engine to be initialized * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * Calling this function ensures that GR engine initialization i.e. * nvgpu_gr_init_support() function call is complete. @@ -234,8 +234,8 @@ void nvgpu_gr_wait_initialized(struct gk20a *g); /** * @brief Set GR s/w ready status. * - * @param g[in] Pointer to GPU driver struct. - * @param enable[in] Boolean flag. + * @param g [in] Pointer to GPU driver struct. + * @param enable [in] Boolean flag. * * This function sets/unsets GR s/w ready status in struct nvgpu_gr. * Setting of flag is typically needed during initialization of GR s/w. @@ -246,7 +246,7 @@ void nvgpu_gr_sw_ready(struct gk20a *g, bool enable); /** * @brief Get number of SMs in GR engine. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function returns number of SMs available in GR engine. * Note that this count is initialized only after GR engine is @@ -259,7 +259,7 @@ u32 nvgpu_gr_get_no_of_sm(struct gk20a *g); /** * @brief Suspend GR engine. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function is typically called while preparing for GPU power off. * This function makes sure that GR engine is idle before power off. @@ -273,7 +273,7 @@ int nvgpu_gr_suspend(struct gk20a *g); /** * @brief Remove GR engine s/w support. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This is typically called while removing entire GPU driver. * This function will ensure that all memory and other system resources @@ -284,8 +284,8 @@ void nvgpu_gr_remove_support(struct gk20a *g); /** * @brief Get base register offset of a given GPC. * - * @param g[in] Pointer to GPU driver struct. - * @param gpc[in] GPC index. + * @param g [in] Pointer to GPU driver struct. + * @param gpc [in] GPC index. * * This function calculates and returns base register offset of a given * GPC. @@ -297,8 +297,8 @@ u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc); /** * @brief Get base register offset of a given TPC in a GPC. * - * @param g[in] Pointer to GPU driver struct. - * @param tpc[in] TPC index. + * @param g [in] Pointer to GPU driver struct. + * @param tpc [in] TPC index. * * This function calculates and returns base register offset of a given * TPC within a GPC. @@ -310,8 +310,8 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc); /** * @brief Get base register offset of a given SM in a GPC/TPC. * - * @param g[in] Pointer to GPU driver struct. - * @param sm[in] SM index. + * @param g [in] Pointer to GPU driver struct. + * @param sm [in] SM index. * * This function calculates and returns base register offset of a given * SM within a GPC/TPC pair. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h index 1e529f98a..f721fd2d0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h @@ -157,7 +157,7 @@ struct nvgpu_fecs_ecc_status { /** * @brief Initialize GR falcon structure. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for #nvgpu_gr_falcon structure and * initializes all mutexes in this structure. @@ -170,8 +170,8 @@ struct nvgpu_gr_falcon *nvgpu_gr_falcon_init_support(struct gk20a *g); /** * @brief Free GR falcon structure. * - * @param g[in] Pointer to GPU driver struct. - * @param falcon[in] Pointer to GR falcon struct. + * @param g [in] Pointer to GPU driver struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will free memory allocated for #nvgpu_gr_falcon * structure. @@ -182,8 +182,8 @@ void nvgpu_gr_falcon_remove_support(struct gk20a *g, /** * @brief Load and boot CTXSW ucodes. * - * @param g[in] Pointer to GPU driver struct. - * @param falcon[in] Pointer to GR falcon struct. + * @param g [in] Pointer to GPU driver struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will load FECS and GPCCS ucodes and bootstrap them * on falcon microcontrollers. This function will also make sure that @@ -200,8 +200,8 @@ int nvgpu_gr_falcon_init_ctxsw(struct gk20a *g, struct nvgpu_gr_falcon *falcon); /** * @brief Initialize context state. * - * @param g[in] Pointer to GPU driver struct. - * @param falcon[in] Pointer to GR falcon struct. + * @param g [in] Pointer to GPU driver struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will query golden context image size from FECS * microcontroller. @@ -214,8 +214,8 @@ int nvgpu_gr_falcon_init_ctx_state(struct gk20a *g, /** * @brief Initialize CTXSW ucodes. * - * @param g[in] Pointer to GPU driver struct. - * @param falcon[in] Pointer to GR falcon struct. + * @param g [in] Pointer to GPU driver struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will read FECS and GPCCS ucodes from filesystem * and fill in details of boot, code, and data segments in @@ -234,8 +234,8 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g, /** * @brief Load and boot CTXSW ucodes in a secure method. * - * @param g[in] Pointer to GPU driver struct. - * @param falcon[in] Pointer to GR falcon struct. + * @param g [in] Pointer to GPU driver struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will load FECS and GPCCS ucodes and bootstrap them * on falcon microcontrollers in a secure method. This function will @@ -250,7 +250,7 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, /** * @brief Get FECS ucode segments pointer. * - * @param falcon[in] Pointer to GR falcon struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will return FECS ucode segment data structure pointer. * All the details of boot/code/data segments are stored in @@ -264,7 +264,7 @@ struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_fecs_ucode_segments( /** * @brief Get GPCCS ucode segments pointer. * - * @param falcon[in] Pointer to GR falcon struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function will return GPCCS ucode segment data structure pointer. * All the details of boot/code/data segments are stored in @@ -278,7 +278,7 @@ struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_gpccs_ucode_segments( /** * @brief Get CPU virtual address of ucode surface. * - * @param falcon[in] Pointer to GR falcon struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function returns CPU virtual address of ucode surface memory * buffer. This buffer is created while reading FECS and GPCCS ucodes @@ -292,7 +292,7 @@ void *nvgpu_gr_falcon_get_surface_desc_cpu_va( /** * @brief Get size of golden context image. * - * @param falcon[in] Pointer to GR falcon struct. + * @param falcon [in] Pointer to GR falcon struct. * * This function returns size of golden context image read from FECS * microcontroller in #nvgpu_gr_falcon_init_ctx_state(). diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h index 0dcf67a61..b4fccba51 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h @@ -40,9 +40,9 @@ struct nvgpu_gr_intr; /** * @brief Handle all FECS error interrupts. * - * @param g[in] Pointer to GPU driver struct. - * @param ch[in] Pointer to GPU channel. - * @param isr_data[in] Pointer to GR ISR data. + * @param g [in] Pointer to GPU driver struct. + * @param ch [in] Pointer to GPU channel. + * @param isr_data [in] Pointer to GR ISR data. * * This function handles all error interrupts coming from * FECS microcontroller. Errors include: @@ -65,11 +65,11 @@ int nvgpu_gr_intr_handle_fecs_error(struct gk20a *g, struct nvgpu_channel *ch, /** * @brief Handle all GPC exception interrupts. * - * @param g[in] Pointer to GPU driver struct. - * @param post_event[out] Flag to post event, ignored for safety. - * @param gr_config[in] Pointer to GR configuration struct. - * @param fault_ch[in] Pointer to faulted GPU channel. - * @param hww_global_esr[out] Global Error Status Register value. + * @param g [in] Pointer to GPU driver struct. + * @param post_event [out] Flag to post event, ignored for safety. + * @param gr_config [in] Pointer to GR configuration struct. + * @param fault_ch [in] Pointer to faulted GPU channel. + * @param hww_global_esr [out] Global Error Status Register value. * * This function handles all exception interrupts coming from * GPC (Graphics Processing Cluster). Interrupts include interrupts @@ -91,8 +91,8 @@ int nvgpu_gr_intr_handle_gpc_exception(struct gk20a *g, bool *post_event, /** * @brief Handle notification interrupt. * - * @param g[in] Pointer to GPU driver struct. - * @param isr_data[in] Pointer to GR ISR data. + * @param g [in] Pointer to GPU driver struct. + * @param isr_data [in] Pointer to GR ISR data. * * This function handles notification interrupt and broadcasts the * notification to waiters. @@ -103,8 +103,8 @@ void nvgpu_gr_intr_handle_notify_pending(struct gk20a *g, /** * @brief Handle semaphore interrupt. * - * @param g[in] Pointer to GPU driver struct. - * @param isr_data[in] Pointer to GR ISR data. + * @param g [in] Pointer to GPU driver struct. + * @param isr_data [in] Pointer to GR ISR data. * * This function handles semaphore release notification interrupt * and broadcasts the notification to waiters. @@ -115,11 +115,11 @@ void nvgpu_gr_intr_handle_semaphore_pending(struct gk20a *g, /** * @brief Report GR exceptions to qnx.sdl unit. * - * @param g[in] Pointer to GPU driver struct. - * @param inst[in] Unit instance ID. - * @param err_type[in] Error type. - * @param status[in] Exception status value. - * @param sub_err_type[in] Sub error type. + * @param g [in] Pointer to GPU driver struct. + * @param inst [in] Unit instance ID. + * @param err_type [in] Error type. + * @param status [in] Exception status value. + * @param sub_err_type [in] Sub error type. * * This function reports all GR exceptions to qnx.sdl unit. * @@ -132,9 +132,9 @@ void nvgpu_gr_intr_report_exception(struct gk20a *g, u32 inst, /** * @brief Translate context to channel ID. * - * @param g[in] Pointer to GPU driver struct. - * @param curr_ctx[in] Context value. - * @param curr_tsgid[out] TSG ID. + * @param g [in] Pointer to GPU driver struct. + * @param curr_ctx [in] Context value. + * @param curr_tsgid [out] TSG ID. * * This function translates given context into corresponding * #nvgpu_channel and TSG identifier. @@ -151,9 +151,9 @@ struct nvgpu_channel *nvgpu_gr_intr_get_channel_from_ctx(struct gk20a *g, /** * @brief Set error notifier for GR errors/exceptions. * - * @param g[in] Pointer to GPU driver struct. - * @param isr_data[in] Pointer to GR ISR data. - * @param error_notifier[in] Error notifier value to be set. + * @param g [in] Pointer to GPU driver struct. + * @param isr_data [in] Pointer to GR ISR data. + * @param error_notifier [in] Error notifier value to be set. * * This function will set #error_notifier error code into TSG's error * notifier (if configured by user application). @@ -167,13 +167,13 @@ void nvgpu_gr_intr_set_error_notifier(struct gk20a *g, /** * @brief Handle all SM exception interrupts. * - * @param g[in] Pointer to GPU driver struct. - * @param gpc[in] Index of GPC on which exception is received. - * @param tpc[in] Index of TPC on which exception is received. - * @param sm[in] Index of SM on which exception is received. - * @param post_event[out] Flag to post event, ignored for safety. - * @param fault_ch[in] Pointer to faulted GPU channel. - * @param hww_global_esr[out] Global Error Status Register value. + * @param g [in] Pointer to GPU driver struct. + * @param gpc [in] Index of GPC on which exception is received. + * @param tpc [in] Index of TPC on which exception is received. + * @param sm [in] Index of SM on which exception is received. + * @param post_event [out] Flag to post event, ignored for safety. + * @param fault_ch [in] Pointer to faulted GPU channel. + * @param hww_global_esr [out] Global Error Status Register value. * * This function handles all exception interrupts coming from * SM (Streaming Multiprocessor). This function will read global and @@ -193,7 +193,7 @@ int nvgpu_gr_intr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, /** * @brief ISR for GR engine stalling interrupts. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This is the entry point to handle all GR engine stalling interrupts. * This includes: @@ -222,7 +222,7 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g); /** * @brief Flush channel lookup TLB. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * common.gr.intr unit maintains a TLB to translate context into GPU * channel ID. See #nvgpu_gr_intr_get_channel_from_ctx() for reference. @@ -235,7 +235,7 @@ void nvgpu_gr_intr_flush_channel_tlb(struct gk20a *g); /** * @brief Initialize GR interrupt data structure. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function allocates memory for #nvgpu_gr_intr structure, and * initializes various fields in the structure. @@ -248,8 +248,8 @@ struct nvgpu_gr_intr *nvgpu_gr_intr_init_support(struct gk20a *g); /** * @brief Free GR interrupt data structure. * - * @param g[in] Pointer to GPU driver struct. - * @param intr[in] Pointer to GR interrupt data struct. + * @param g [in] Pointer to GPU driver struct. + * @param intr [in] Pointer to GR interrupt data struct. * * This function will free memory allocated for #nvgpu_gr_intr structure. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h index 987e48751..108ecd009 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h @@ -52,8 +52,8 @@ struct nvgpu_gr_global_ctx_buffer_desc; /** * @brief Compute checksum. * - * @param a[in] First unsigned integer. - * @param b[in] Second unsigned integer. + * @param a [in] First unsigned integer. + * @param b [in] Second unsigned integer. * * This function will calculate checksum of two unsigned integers and * return the result. This function is typically needed to calculate @@ -66,7 +66,7 @@ u32 nvgpu_gr_checksum_u32(u32 a, u32 b); /** * @brief Get GR falcon data struct pointer. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function returns pointer to #nvgpu_gr_falcon structure. * @@ -77,7 +77,7 @@ struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g); /** * @brief Get GR configuration struct pointer. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function returns pointer to #nvgpu_gr_config structure. * @@ -88,7 +88,7 @@ struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g); /** * @brief Get GR interrupt data struct pointer. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function returns pointer to #nvgpu_gr_intr structure. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h index bf1a5af51..402196f5f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h @@ -52,9 +52,9 @@ struct nvgpu_gr_obj_ctx_golden_image; /** * @brief Commit context buffer address in instance block. * - * @param g[in] Pointer to GPU driver struct. - * @param inst_block[in] Pointer to channel instance block. - * @param gpu_va[in] GPU virtual address to be committed. + * @param g [in] Pointer to GPU driver struct. + * @param inst_block [in] Pointer to channel instance block. + * @param gpu_va [in] GPU virtual address to be committed. * * This function will commit given GPU virtual address into given * channel instance block. Appropriate address is selected by @@ -66,11 +66,11 @@ void nvgpu_gr_obj_ctx_commit_inst_gpu_va(struct gk20a *g, /** * @brief Commit context buffer in instance block. * - * @param g[in] Pointer to GPU driver struct. - * @param inst_block[in] Pointer to channel instance block. - * @param gr_ctx[in] Pointer to graphics context buffer. - * @param subctx[in] Pointer to graphics subcontext buffer. - * @param gpu_va[in] GPU virtual address of graphics context buffer. + * @param g [in] Pointer to GPU driver struct. + * @param inst_block [in] Pointer to channel instance block. + * @param gr_ctx [in] Pointer to graphics context buffer. + * @param subctx [in] Pointer to graphics subcontext buffer. + * @param gpu_va [in] GPU virtual address of graphics context buffer. * * If graphics subcontexts are supported, subcontext buffer GPU virtual * address should be committed to channel instance block. Otherwise graphics @@ -87,12 +87,12 @@ void nvgpu_gr_obj_ctx_commit_inst(struct gk20a *g, struct nvgpu_mem *inst_block, /** * brief Initialize preemption mode in context struct. * - * @param g[in] Pointer to GPU driver struct. - * @param config[in] Pointer to GR configuration struct. - * @param gr_ctx_desc[in] Pointer to GR context descriptor struct. - * @param gr_ctx[in] Pointer to graphics context. - * @param vm[in] Pointer to virtual memory. - * @param class_num[in] GR engine class. + * @param g [in] Pointer to GPU driver struct. + * @param config [in] Pointer to GR configuration struct. + * @param gr_ctx_desc [in] Pointer to GR context descriptor struct. + * @param gr_ctx [in] Pointer to graphics context. + * @param vm [in] Pointer to virtual memory. + * @param class_num [in] GR engine class. * @param graphics_preempt_mode Graphics preemption mode to set. * @param compute_preempt_mode Compute preemption mode to set. * @@ -115,10 +115,10 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g, /** * brief Update preemption mode in graphics context buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param config[in] Pointer to GR configuration struct. - * @param gr_ctx[in] Pointer to graphics context. - * @param subctx[in] Pointer to graphics subcontext buffer. + * @param g [in] Pointer to GPU driver struct. + * @param config [in] Pointer to GR configuration struct. + * @param gr_ctx [in] Pointer to graphics context. + * @param subctx [in] Pointer to graphics subcontext buffer. * * This function will read preemption modes stored in #nvgpu_gr_ctx * struct and write them into graphics context image. @@ -134,11 +134,11 @@ void nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(struct gk20a *g, /** * brief Update global context buffer addresses in graphics context. * - * @param g[in] Pointer to GPU driver struct. - * @param global_ctx_buffer[in] Pointer to global context descriptor struct. - * @param config[in] Pointer to GR configuration struct. - * @param gr_ctx[in] Pointer to graphics context. - * @param patch[in] Boolean flag to use patch context buffer. + * @param g [in] Pointer to GPU driver struct. + * @param global_ctx_buffer [in] Pointer to global context descriptor struct. + * @param config [in] Pointer to GR configuration struct. + * @param gr_ctx [in] Pointer to graphics context. + * @param patch [in] Boolean flag to use patch context buffer. * * This function will update GPU virtual addresses of global context * buffers in given graphics context image. @@ -155,12 +155,12 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g, /** * @brief Allocate golden context image. * - * @param g[in] Pointer to GPU driver struct. - * @param golden_image[in] Pointer to golden context image struct. - * @param global_ctx_buffer[in] Pointer to global context descriptor struct. - * @param config[in] Pointer to GR configuration struct. - * @param gr_ctx[in] Pointer to graphics context. - * @param inst_block[in] Pointer to channel instance block. + * @param g [in] Pointer to GPU driver struct. + * @param golden_image [in] Pointer to golden context image struct. + * @param global_ctx_buffer [in] Pointer to global context descriptor struct. + * @param config [in] Pointer to GR configuration struct. + * @param gr_ctx [in] Pointer to graphics context. + * @param inst_block [in] Pointer to channel instance block. * * This function allocates golden context image. * @@ -194,19 +194,19 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g, /** * @brief Allocate object context. * - * @param g[in] Pointer to GPU driver struct. - * @param golden_image[in] Pointer to golden context image struct. - * @param global_ctx_buffer[in] Pointer to global context descriptor struct. - * @param gr_ctx_desc[in] Pointer to GR context descriptor struct. - * @param config[in] Pointer to GR configuration struct. - * @param gr_ctx[in] Pointer to graphics context. - * @param subctx[in] Pointer to graphics subcontext buffer. - * @param vm[in] Pointer to virtual memory. - * @param inst_block[in] Pointer to channel instance block. - * @param class_num[in] GR engine class. - * @param flags[in] Object context attribute flags. - * @param cde[in] Boolean flag to enable/disable CDE. - * @param vpr[in] Boolean flag to use global context buffers + * @param g [in] Pointer to GPU driver struct. + * @param golden_image [in] Pointer to golden context image struct. + * @param global_ctx_buffer [in] Pointer to global context descriptor struct. + * @param gr_ctx_desc [in] Pointer to GR context descriptor struct. + * @param config [in] Pointer to GR configuration struct. + * @param gr_ctx [in] Pointer to graphics context. + * @param subctx [in] Pointer to graphics subcontext buffer. + * @param vm [in] Pointer to virtual memory. + * @param inst_block [in] Pointer to channel instance block. + * @param class_num [in] GR engine class. + * @param flags [in] Object context attribute flags. + * @param cde [in] Boolean flag to enable/disable CDE. + * @param vpr [in] Boolean flag to use global context buffers * allocated in VPR. * * This function allocates object context for the GPU channel. @@ -245,8 +245,8 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g, /** * @brief Set golden context image size. * - * @param golden_image[in] Pointer to golden context image struct. - * @param size[in] Size to be set. + * @param golden_image [in] Pointer to golden context image struct. + * @param size [in] Size to be set. * * This function sets given size in #nvgpu_gr_obj_ctx_golden_image * struct. @@ -258,7 +258,7 @@ void nvgpu_gr_obj_ctx_set_golden_image_size( /** * @brief Get golden context image size. * - * @param golden_image[in] Pointer to golden context image struct. + * @param golden_image [in] Pointer to golden context image struct. * * This function returns size of golden context image stored in * #nvgpu_gr_obj_ctx_golden_image struct. @@ -271,7 +271,7 @@ size_t nvgpu_gr_obj_ctx_get_golden_image_size( /** * @brief Check if golden context image is ready. * - * @param golden_image[in] Pointer to golden context image struct. + * @param golden_image [in] Pointer to golden context image struct. * * This function checks if golden context image has been allocated * and initialized. @@ -288,8 +288,8 @@ bool nvgpu_gr_obj_ctx_is_golden_image_ready( /** * @brief Initialize object context. * - * @param gr_golden_image[in] Pointer to golden context image struct. - * @param size[in] Size to be set. + * @param gr_golden_image [in] Pointer to golden context image struct. + * @param size [in] Size to be set. * * This function allocates memory for #nvgpu_gr_obj_ctx_golden_image * struct and sets given size in it. @@ -303,7 +303,7 @@ int nvgpu_gr_obj_ctx_init(struct gk20a *g, /** * @brief Deinitialize object context. * - * @param golden_image[in] Pointer to golden context image struct. + * @param golden_image [in] Pointer to golden context image struct. * * This function will free memory allocated for local golden context * image and also for #nvgpu_gr_obj_ctx_golden_image struct. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h index 438cfec4e..bc8fea47e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/setup.h @@ -37,9 +37,9 @@ struct nvgpu_gr_ctx; /** * @brief Allocate and setup object context s/w image for GPU channel. * - * @param c[in] Pointer to GPU channel. - * @param class_num[in] GPU class ID. - * @param flags[in] Flags for context allocation. + * @param c [in] Pointer to GPU channel. + * @param class_num [in] GPU class ID. + * @param flags [in] Flags for context allocation. * * This function allocates and sets up object context for a GPU channel. * The steps include: @@ -65,9 +65,9 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, /** * @brief Free GR engine context image. * - * @param g[in] Pointer to GPU driver struct. - * @param vm[in] Pointer to virtual memory. - * @param gr_ctx[in] Pointer to GR engine context image. + * @param g [in] Pointer to GPU driver struct. + * @param vm [in] Pointer to virtual memory. + * @param gr_ctx [in] Pointer to GR engine context image. * * This function will free memory allocated for patch context image and * GR engine context image in #nvgpu_gr_setup_alloc_obj_ctx(). @@ -78,7 +78,7 @@ void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, /** * @brief Free GR engine subcontext. * - * @param c[in] Pointer to GPU channel. + * @param c [in] Pointer to GPU channel. * * This function will free memory allocated for GR engine subcontext * image in #nvgpu_gr_setup_alloc_obj_ctx(). @@ -88,9 +88,9 @@ void nvgpu_gr_setup_free_subctx(struct nvgpu_channel *c); /** * @brief Setup preemption mode in GR engine context image. * - * @param ch[in] Pointer to GPU channel. - * @param graphics_preempt_mode[in] Requested graphics preemption mode. - * @param compute_preempt_mode[in] Requested compute preemption mode. + * @param ch [in] Pointer to GPU channel. + * @param graphics_preempt_mode [in] Requested graphics preemption mode. + * @param compute_preempt_mode [in] Requested compute preemption mode. * * This function will program newly requested preemption modes into * GR engine context image. This function is typically needed if user diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h index c602ee9fd..4efa48742 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h @@ -38,8 +38,8 @@ struct nvgpu_mem; /** * @brief Allocate graphics subcontext buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param vm[in] Pointer to virtual memory. + * @param g [in] Pointer to GPU driver struct. + * @param vm [in] Pointer to virtual memory. * * This function allocates memory for #nvgpu_gr_subctx structure * and subcontext header stored in #nvgpu_gr_subctx structure. @@ -56,9 +56,9 @@ struct nvgpu_gr_subctx *nvgpu_gr_subctx_alloc(struct gk20a *g, /** * @brief Free graphics subcontext buffer. * - * @param g[in] Pointer to GPU driver struct. - * @param subctx[in] Pointer to graphics subcontext struct. - * @param vm[in] Pointer to virtual memory. + * @param g [in] Pointer to GPU driver struct. + * @param subctx [in] Pointer to graphics subcontext struct. + * @param vm [in] Pointer to virtual memory. * * This function will free memory allocated for subcontext header and * #nvgpu_gr_subctx structure. @@ -70,10 +70,10 @@ void nvgpu_gr_subctx_free(struct gk20a *g, /** * @brief Initialize graphics subcontext buffer header. * - * @param g[in] Pointer to GPU driver struct. - * @param subctx[in] Pointer to graphics subcontext struct. - * @param gr_ctx[in] Pointer to graphics context struct. - * @param gpu_va[in] GPU virtual address of graphics context buffer. + * @param g [in] Pointer to GPU driver struct. + * @param subctx [in] Pointer to graphics subcontext struct. + * @param gr_ctx [in] Pointer to graphics context struct. + * @param gpu_va [in] GPU virtual address of graphics context buffer. * * This function will initialize graphics subcontext buffer header * by reading appropriate values from #nvgpu_gr_ctx structure and @@ -89,9 +89,9 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, /** * @brief Set patch context buffer address in subcontext header. * - * @param g[in] Pointer to GPU driver struct. - * @param subctx[in] Pointer to graphics subcontext struct. - * @param gr_ctx[in] Pointer to graphics context struct. + * @param g [in] Pointer to GPU driver struct. + * @param subctx [in] Pointer to graphics subcontext struct. + * @param gr_ctx [in] Pointer to graphics context struct. * * This function will program GPU virtual address of patch context buffer * into subcontext buffer header. @@ -102,7 +102,7 @@ void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g, /** * @brief Get pointer of subcontext header memory struct. * - * @param subctx[in] Pointer to graphics subcontext struct. + * @param subctx [in] Pointer to graphics subcontext struct. * * This function returns #nvgpu_mem pointer of subcontext header stored * in #nvgpu_gr_subctx. diff --git a/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h b/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h index 83fa9c87f..26c6823a6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h +++ b/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h @@ -31,7 +31,7 @@ /** * @brief Write a value to an usermode mapped io-region. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * @param r [in] Register offset in io-region. * @param v [in] Value to write at the offset. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/ltc.h index 88c246960..7e71b6d44 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ltc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ltc.h @@ -117,7 +117,7 @@ u32 nvgpu_ltc_get_slices_per_ltc(struct gk20a *g); /** * @brief Get cacheline size. * - * @param g[in] Pointer to GPU driver struct. + * @param g [in] Pointer to GPU driver struct. * * This function returns cacheline size in bytes. * Cacheline is chunk of memory that can be handled in one go by cache. diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h index a47a72bbb..e5b1f5247 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h @@ -37,7 +37,7 @@ struct gk20a; /** * @brief Initialize PBDMA software context * - * @param g[in] The GPU driver struct for which to initialize + * @param g [in] The GPU driver struct for which to initialize * PBDMA software context. * * Gets number of PBDMAs and builds a map of runlists that will be serviced @@ -51,7 +51,7 @@ int nvgpu_pbdma_setup_sw(struct gk20a *g); /** * @brief Clean up PBDMA software context * - * @param g[in] The GPU driver struct using PBDMA software + * @param g [in] The GPU driver struct using PBDMA software * context. * * Cleans up PBDMA software context and related resources. @@ -61,9 +61,9 @@ void nvgpu_pbdma_cleanup_sw(struct gk20a *g); /** * @brief Find PBDMA servicing the runlist * - * @param g[in] The GPU driver struct owning the runlist. - * @param runlist_id[in] Runlist identifier. - * @param pbdma_id[out] Pointer to PBDMA identifier. + * @param g [in] The GPU driver struct owning the runlist. + * @param runlist_id [in] Runlist identifier. + * @param pbdma_id [out] Pointer to PBDMA identifier. * * Finds the PBDMA which is servicing #runlist_id. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h index 2192d9dca..519afa7d5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h @@ -109,7 +109,7 @@ struct nvgpu_pbdma_status_info { /** * @brief Check if chsw_status is set to switch. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if channel @@ -120,7 +120,7 @@ bool nvgpu_pbdma_status_is_chsw_switch(struct nvgpu_pbdma_status_info /** * @brief Check if chsw_status is set to load. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if channel @@ -131,7 +131,7 @@ bool nvgpu_pbdma_status_is_chsw_load(struct nvgpu_pbdma_status_info /** * @brief Check if chsw_status is set to save. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if channel @@ -142,7 +142,7 @@ bool nvgpu_pbdma_status_is_chsw_save(struct nvgpu_pbdma_status_info /** * @brief Check if chsw_status is set to valid. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if channel @@ -153,7 +153,7 @@ bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info /** * @brief Check if id_type is tsg. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if id_type @@ -164,7 +164,7 @@ bool nvgpu_pbdma_status_is_id_type_tsg(struct nvgpu_pbdma_status_info /** * @brief Check if next_id_type is tsg. * - * @param pbdma_status[in] Pointer to struct containing pbdma_status h/w + * @param pbdma_status [in] Pointer to struct containing pbdma_status h/w * reg/field value. * * @return Interprets #pbdma_status and returns true if next_id_type diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h index d75fc50de..3c9f0a5a2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h @@ -147,7 +147,7 @@ struct nvgpu_fifo; /** * @brief Load register configuration for ELCG and BLCG for GR related modules. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capabilities slcg_enabled and blcg_enabled and * programs registers for configuring production gating values for ELCG & BLCG. @@ -159,7 +159,7 @@ void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g); /** * @brief Enable ELCG for engines without waiting for GR init to complete. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability elcg_enabled and programs the * engine gate_ctrl registers with ELCG_AUTO mode configuration. @@ -169,7 +169,7 @@ void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g); /** * @brief Disable ELCG for engines without waiting for GR init to complete. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability elcg_enabled and programs the * engine gate_ctrl registers with ELCG_RUN mode configuration. @@ -179,7 +179,7 @@ void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g); /** * @brief Load register configuration for BLCG for FB and LTC. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability blcg_enabled and programs registers * for configuring production gating values for BLCG for FB and LTC. @@ -189,7 +189,7 @@ void nvgpu_cg_blcg_fb_ltc_load_enable(struct gk20a *g); /** * @brief Load register configuration for BLCG for FIFO. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability blcg_enabled and programs registers * for configuring production gating values for BLCG for FIFO. @@ -199,7 +199,7 @@ void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g); /** * @brief Load register configuration for BLCG for PMU. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability blcg_enabled and programs registers * for configuring production gating values for BLCG for PMU. @@ -209,7 +209,7 @@ void nvgpu_cg_blcg_pmu_load_enable(struct gk20a *g); /** * @brief Load register configuration for BLCG for CE. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability blcg_enabled and programs registers * for configuring production gating values for BLCG for CE. @@ -219,7 +219,7 @@ void nvgpu_cg_blcg_ce_load_enable(struct gk20a *g); /** * @brief Load register configuration for BLCG for GR. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability blcg_enabled and programs registers * for configuring production gating values for BLCG for GR. @@ -229,7 +229,7 @@ void nvgpu_cg_blcg_gr_load_enable(struct gk20a *g); /** * @brief Load register configuration for SLCG for FB and LTC. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability slcg_enabled and programs registers * for configuring production gating values for SLCG for FB and LTC. @@ -239,7 +239,7 @@ void nvgpu_cg_slcg_fb_ltc_load_enable(struct gk20a *g); /** * @brief Load register configuration for SLCG for PRIV RING. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability slcg_enabled and programs registers * for configuring production gating values for SLCG for PRIV RING. @@ -249,7 +249,7 @@ void nvgpu_cg_slcg_priring_load_enable(struct gk20a *g); /** * @brief Load register configuration for SLCG for FIFO. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability slcg_enabled and programs registers * for configuring production gating values for SLCG for FIFO. @@ -259,7 +259,7 @@ void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g); /** * @brief Load register configuration for SLCG for PMU. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability slcg_enabled and programs registers * for configuring production gating values for SLCG for PMU. @@ -269,7 +269,7 @@ void nvgpu_cg_slcg_pmu_load_enable(struct gk20a *g); /** * @brief Load register configuration for SLCG for CE2. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Checks the platform software capability slcg_enabled and programs registers * for configuring production gating values for SLCG for CE2. diff --git a/drivers/gpu/nvgpu/include/nvgpu/preempt.h b/drivers/gpu/nvgpu/include/nvgpu/preempt.h index 2cfa7cd38..23724e105 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/preempt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/preempt.h @@ -36,7 +36,7 @@ struct nvgpu_tsg; /** * @brief Get preemption timeout (ms). This timeout is defined by s/w. * - * @param g[in] The GPU driver struct to query preempt timeout for. + * @param g [in] The GPU driver struct to query preempt timeout for. * * @return Maximum amount of time in ms to wait for preemption completion, * i.e. context non resident on PBDMAs and engines. @@ -46,8 +46,8 @@ u32 nvgpu_preempt_get_timeout(struct gk20a *g); /** * @brief Preempts TSG if channel is bound to TSG. * - * @param g[in] The GPU driver struct which owns this channel. - * @param ch[in] Pointer to channel to be preempted. + * @param g [in] The GPU driver struct which owns this channel. + * @param ch [in] Pointer to channel to be preempted. * * Preempts TSG if channel is bound to TSG. Preemption implies that the * context's state is saved out and also that the context cannot remain parked diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h index a630c94f5..601d9c37f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h @@ -98,10 +98,10 @@ struct nvgpu_runlist_info { /** * @brief Rebuild runlist * - * @param f[in] The FIFO context using this runlist. - * @param runlist[in] Runlist context. - * @param buf_id[in] Indicates which runlist buffer to use. - * @param max_entries[in] Max number of entries in runlist buffer. + * @param f [in] The FIFO context using this runlist. + * @param runlist [in] Runlist context. + * @param buf_id [in] Indicates which runlist buffer to use. + * @param max_entries [in] Max number of entries in runlist buffer. * * Walks through all active TSGs in #runlist, and constructs runlist * buffer #buf_id. This buffer can afterwards be submitted to H/W @@ -120,11 +120,11 @@ u32 nvgpu_runlist_construct_locked(struct nvgpu_fifo *f, /** * @brief Add/remove channel to/from runlist (locked) * - * @param g[in] The GPU driver struct owning this runlist. - * @param runlist_id[in] Runlist identifier. - * @param ch[in] Channel to be added/removed or NULL. - * @param add[in] True to add a channel, false to remove it. - * @param wait_for_finish[in] True to wait for runlist update completion. + * @param g [in] The GPU driver struct owning this runlist. + * @param runlist_id [in] Runlist identifier. + * @param ch [in] Channel to be added/removed or NULL. + * @param add [in] True to add a channel, false to remove it. + * @param wait_for_finish [in] True to wait for runlist update completion. * * When #ch is NULL, this function has same behavior as #nvgpu_runlist_reload. * When #ch is non NULL, this function has same behavior as @@ -148,11 +148,11 @@ int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next, /** * @brief Add/remove channel to/from runlist * - * @param g[in] The GPU driver struct owning this runlist. - * @param runlist_id[in] Runlist identifier - * @param ch[in] Channel to be added/removed (must be non NULL) - * @param add[in] True to add channel to runlist - * @param wait_for_finish[in] True to wait for completion + * @param g [in] The GPU driver struct owning this runlist. + * @param runlist_id [in] Runlist identifier + * @param ch [in] Channel to be added/removed (must be non NULL) + * @param add [in] True to add channel to runlist + * @param wait_for_finish [in] True to wait for completion * * When #add is true, adds #ch to active channels of runlist #runlist_id. * When #add is false, removes #ch from active channels of runlist #runlist_id. @@ -177,12 +177,12 @@ int nvgpu_runlist_update_for_channel(struct gk20a *g, u32 runlist_id, /** * @brief Reload runlist * - * @param g[in] The GPU driver struct owning this runlist. - * @param runlist_id[in] Runlist identifier. - * @param add[in] True to submit a runlist buffer with all active + * @param g [in] The GPU driver struct owning this runlist. + * @param runlist_id [in] Runlist identifier. + * @param add [in] True to submit a runlist buffer with all active * channels. False to submit an empty runlist * buffer. - * @param wait_for_finish[in] True to wait for runlist update completion. + * @param wait_for_finish [in] True to wait for runlist update completion. * * When #add is true, all entries are updated for the runlist. A runlist buffer * is built with all active channels/TSGs for the runlist and submitted to H/W. @@ -203,9 +203,9 @@ int nvgpu_runlist_reload(struct gk20a *g, u32 runlist_id, /** * @brief Reload a set of runlists * - * @param g[in] The GPU driver struct owning the runlists. - * @param runlist_ids[in] Bitmask of runlists, one bit per runlist_id. - * @param add[in] True to submit a runlist buffer with all active + * @param g [in] The GPU driver struct owning the runlists. + * @param runlist_ids [in] Bitmask of runlists, one bit per runlist_id. + * @param add [in] True to submit a runlist buffer with all active * channels. False to submit an empty runlist * buffer. * @@ -232,9 +232,9 @@ const char *nvgpu_runlist_interleave_level_name(u32 interleave_level); /** * @brief Enable/disable a set of runlists * - * @param g[in] The GPU driver struct owning the runlists. - * @param runlist_mask[in] Bitmask of runlist, one bit per runlist_id. - * @param runlist_state[in] #RUNLIST_ENABLE or #RUNLIST_DISABLE. + * @param g [in] The GPU driver struct owning the runlists. + * @param runlist_mask [in] Bitmask of runlist, one bit per runlist_id. + * @param runlist_state [in] #RUNLIST_ENABLE or #RUNLIST_DISABLE. * * If scheduling of a runlist is disabled, no new channels will be scheduled * to run from that runlist. It does not stop the scheduler from finishing @@ -251,7 +251,7 @@ void nvgpu_runlist_set_state(struct gk20a *g, u32 runlists_mask, /** * @brief Initialize runlist context * - * @param g[in] The GPU driver struct owning the runlists. + * @param g [in] The GPU driver struct owning the runlists. * * Initializes runlist context for current GPU: * - Determine number of runlists and max entries per runlists. @@ -271,7 +271,7 @@ int nvgpu_runlist_setup_sw(struct gk20a *g); /** * @brief De-initialize runlist context * - * @param g[in] The GPU driver struct owning the runlists. + * @param g [in] The GPU driver struct owning the runlists. * * Cleans up runlist context for current GPU: * - Free runlist buffers. @@ -283,7 +283,7 @@ void nvgpu_runlist_cleanup_sw(struct gk20a *g); /** * @brief Acquire lock for active runlists * - * @param g[in] The GPU driver struct owning the runlists. + * @param g [in] The GPU driver struct owning the runlists. * * Walk through runlist ids, and acquire runlist lock for runlists that are * actually in use (i.e. mapped to one engine). @@ -293,7 +293,7 @@ void nvgpu_runlist_lock_active_runlists(struct gk20a *g); /** * @brief Release lock for active runlists * - * @param g[in] The GPU driver struct owning the runlists. + * @param g [in] The GPU driver struct owning the runlists. * * Walk through runlist ids, and release runlist lock for runlists that are * actually in use (i.e. mapped to one engine). @@ -303,8 +303,8 @@ void nvgpu_runlist_unlock_active_runlists(struct gk20a *g); /** * @brief Release lock for a set of runlists * - * @param g[in] The GPU driver struct owning the runlists. - * @param runlists_mask[in] Set of runlists to release lock for. One bit + * @param g [in] The GPU driver struct owning the runlists. + * @param runlists_mask [in] Set of runlists to release lock for. One bit * per runlist_id. * * Walk through runlist ids, and release runlist lock for runlists that are @@ -315,13 +315,13 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask); /** * @brief Get list of runlists per engine/PBDMA/TSG * - * @param g[in] The GPU driver struct owning the runlists. - * @param id[in] TSG or Channel Identifier (see #id_type). - * @param id_type[in] Identifier Type (#ID_TYPE_CHANNEL, #ID_TYPE_TSG + * @param g [in] The GPU driver struct owning the runlists. + * @param id [in] TSG or Channel Identifier (see #id_type). + * @param id_type [in] Identifier Type (#ID_TYPE_CHANNEL, #ID_TYPE_TSG * or #ID_TYPE_UNKNOWN). - * @param act_eng_bitmask[in] Bitmask of active engines, one bit per + * @param act_eng_bitmask [in] Bitmask of active engines, one bit per * engine id. - * @param pbdma_bitmask[in] Bitmask of PBDMAs, one bit per PBDMA id. + * @param pbdma_bitmask [in] Bitmask of PBDMAs, one bit per PBDMA id. * * If engines or PBDMAs are known (i.e. non-zero #act_eng_bitmask and/or * #pbdma_bitmask), the function looks up for all runlists servicing those diff --git a/drivers/gpu/nvgpu/include/nvgpu/soc.h b/drivers/gpu/nvgpu/include/nvgpu/soc.h index fd03d01df..cd9c9d426 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/soc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/soc.h @@ -29,7 +29,7 @@ struct gk20a; /** * @brief Check whether running on silicon or not. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Extract out platform info by calling NvTegraSysGetPlatform(). * - If info is NULL return false. @@ -42,7 +42,7 @@ bool nvgpu_platform_is_silicon(struct gk20a *g); /** * @brief Check whether running simulation or not. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Read CPU type by calling NvTegraSysGetCpuType(). * - Read platform info by calling NvTegraSysGetPlatform(). @@ -59,7 +59,7 @@ bool nvgpu_platform_is_simulation(struct gk20a *g); /** * @brief Check whether running fpga or not. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Get tegra Platform info using NvTegraSysGetPlatform(). * - Return false if return info is NULL. @@ -73,7 +73,7 @@ bool nvgpu_platform_is_fpga(struct gk20a *g); /** * @brief Check whether running in virtualized environment. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Return true if NvHvCheckOsNative() is successful. * @@ -84,7 +84,7 @@ bool nvgpu_is_hypervisor_mode(struct gk20a *g); /** * @brief Check whether bpmp server is runing. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * @return Returns true if bpmp server is running else returns false. */ @@ -93,7 +93,7 @@ bool nvgpu_is_bpmp_running(struct gk20a *g); /** * @brief Check whether soc is t194 and revision a01. * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Return true only if NvTegraSysGetChipId() is equal to TEGRA_CHIPID_TEGRA19 * and NvTegraSysGetChipRevision() is equal to TEGRA_REVISION_A01. @@ -104,7 +104,7 @@ bool nvgpu_is_soc_t194_a01(struct gk20a *g); /** * @brief Do soc related init * - * @param g[in] GPU super structure. + * @param g [in] GPU super structure. * * - Set VMID_UNINITIALIZED to r->gid. * - Check if nvgpu_is_hypervisor_mode is enabled if yes then @@ -117,7 +117,7 @@ int nvgpu_init_soc_vars(struct gk20a *g); /** * @brief OS specific implementation to provide precise microsecond delay * - * @param usecs[in] Delay in microseconds. + * @param usecs [in] Delay in microseconds. * * - Wait using nanospin_ns until usecs expires. Log error if API returns non * zero value once wait time expires. diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index 1dc5bef0f..913ad9b37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h @@ -199,8 +199,8 @@ int nvgpu_tsg_open_common(struct gk20a *g, struct nvgpu_tsg *tsg, pid_t pid); /** * @brief Open and initialize unused TSG * - * @param g[in] The GPU driver struct. - * @param pid[in] The PID of the process. + * @param g [in] The GPU driver struct. + * @param pid [in] The PID of the process. * * - Acquire unused TSG. * - Set s/w context of the acquired TSG. @@ -216,8 +216,8 @@ struct nvgpu_tsg *nvgpu_tsg_open(struct gk20a *g, pid_t pid); /** * @brief Clean up resources used by tsg. This is needed for releasing TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. * * - Call non-NULL HAL to release tsg. This HAL is non-NULL for vgpu only. * - Call nvgpu_free_gr_ctx_struct to free #nvgpu_tsg.gr_ctx. @@ -232,7 +232,7 @@ void nvgpu_tsg_release_common(struct gk20a *g, struct nvgpu_tsg *tsg); /** * @brief Release TSG to the pool of free TSGs. * - * @param ref[in] Pointer to #nvgpu_tsg.refcount. + * @param ref [in] Pointer to #nvgpu_tsg.refcount. * * - Get pointer to the #nvgpu_tsg using #ref. * - Call HAL to free #nvgpu_tsg.gr_ctx if this memory pointer is non-NULL @@ -251,7 +251,7 @@ void nvgpu_tsg_release(struct nvgpu_ref *ref); /** * @brief Initialize s/w context for TSGs. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Initialize s/w context for TSGs: * - Allocate zero initialized kernel memory area for #nvgpu_fifo.num_channels @@ -269,7 +269,7 @@ int nvgpu_tsg_setup_sw(struct gk20a *g); /** * @brief De-initialize s/w context for TSGs. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * De-initialize s/w context for TSGs: * - Destroy s/w context for all tsgid starting from 0 to @@ -282,7 +282,7 @@ void nvgpu_tsg_cleanup_sw(struct gk20a *g); /** * @brief Get pointer to #nvgpu_tsg for the tsgid of the given Channel. * - * @param ch[in] Pointer to Channel struct. + * @param ch [in] Pointer to Channel struct. * * Validate tsgid of the given channel. If tsgid is not equal to * #NVGPU_INVALID_TSG_ID, get pointer to area of memory, reserved for s/w @@ -297,7 +297,7 @@ struct nvgpu_tsg *nvgpu_tsg_from_ch(struct nvgpu_channel *ch); /** * @brief Disable all the channels bound to a TSG. * - * @param tsg[in] Pointer to TSG struct. + * @param tsg [in] Pointer to TSG struct. * * Disable all the channels bound to a TSG so that h/w scheduler does not * schedule these channels. @@ -307,8 +307,8 @@ void nvgpu_tsg_disable(struct nvgpu_tsg *tsg); /** * @brief Bind a channel to the TSG. * - * @param tsg[in] Pointer to TSG struct. - * @param ch[in] Pointer to Channel struct. + * @param tsg [in] Pointer to TSG struct. + * @param ch [in] Pointer to Channel struct. * * - Make sure channel is not already bound to a TSG. * - Make sure channel is not part of any runlists. @@ -337,8 +337,8 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, /** * @brief Get pointer to #nvgpu_tsg for the tsgid. * - * @param g[in] The GPU driver struct. - * @param tsgid[in] Id of the TSG. + * @param g [in] The GPU driver struct. + * @param tsgid [in] Id of the TSG. * * Get pointer to area of memory, reserved for s/w context of TSG * and indexed by tsgid. @@ -350,8 +350,8 @@ struct nvgpu_tsg *nvgpu_tsg_get_from_id(struct gk20a *g, u32 tsgid); /** * @brief Validate tsgid and get pointer to #nvgpu_tsg for this tsgid. * - * @param g[in] The GPU driver struct. - * @param tsgid[in] Id of the TSG. + * @param g [in] The GPU driver struct. + * @param tsgid [in] Id of the TSG. * * If tsgid is not equal to #NVGPU_INVALID_TSG_ID, get pointer to area of * memory, reserved for s/w context of TSG and indexed by tsgid. @@ -364,8 +364,8 @@ struct nvgpu_tsg *nvgpu_tsg_check_and_get_from_id(struct gk20a *g, u32 tsgid); /** * @brief Unbind a channel from the TSG it is bound to. * - * @param tsg[in] Pointer to TSG struct. - * @param ch[in] Pointer to Channel struct. + * @param tsg [in] Pointer to TSG struct. + * @param ch [in] Pointer to Channel struct. * * Unbind channel from TSG: * - Check if channel being unbound has become unserviceable. @@ -400,8 +400,8 @@ int nvgpu_tsg_unbind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch); /** * @brief Check h/w channel status before unbinding Channel. * - * @param tsg[in] Pointer to TSG struct. - * @param ch[in] Pointer to Channel struct. + * @param tsg [in] Pointer to TSG struct. + * @param ch [in] Pointer to Channel struct. * * - Call HAL to read chip specific h/w channel status register into hw_state * local variable. @@ -425,9 +425,9 @@ int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg, * @brief Find another channel in the TSG and force ctx reload if * h/w channel status of the channel is set to ctx_reload. * - * @param tsg[in] Pointer to TSG struct. - * @param ch[in] Pointer to Channel struct. - * @param hw_state[in] Pointer to nvgpu_channel_hw_state struct. + * @param tsg [in] Pointer to TSG struct. + * @param ch [in] Pointer to Channel struct. + * @param hw_state [in] Pointer to nvgpu_channel_hw_state struct. * * Find another channel in the TSG and force ctx reload. * @@ -447,8 +447,8 @@ void nvgpu_tsg_post_event_id(struct nvgpu_tsg *tsg, /** * @brief Set mmu fault error notifier for all the channels bound to a TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. * * Set mmu fault error notifier for all the channels bound to the TSG. */ @@ -458,8 +458,8 @@ void nvgpu_tsg_set_ctx_mmu_error(struct gk20a *g, /** * @brief Mark error for all the referenceable channels of tsg's channel list. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. * * - Set verbose local variable to false. * - Acquire #nvgpu_tsg.ch_list_lock of the tsg. @@ -490,7 +490,7 @@ int nvgpu_tsg_set_interleave(struct nvgpu_tsg *tsg, u32 level); /** * @brief Get default TSG timeslice in us as defined by nvgpu driver. * - * @param g[in] The GPU driver struct. + * @param g [in] The GPU driver struct. * * Get TSG timeslice value in microseconds. This is the default timeslice * value in us as defined by s/w. @@ -503,8 +503,8 @@ u32 nvgpu_tsg_default_timeslice_us(struct gk20a *g); * @brief Enable h/w runlist scheduler corresponding to the runlist_id * of the TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to the TSG struct. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to the TSG struct. * * Enable h/w runlist scheduler for #nvgpu_tsg.runlist_id. */ @@ -514,8 +514,8 @@ void nvgpu_tsg_enable_sched(struct gk20a *g, struct nvgpu_tsg *tsg); * @brief Disable h/w runlist scheduler corresponding to the runlist_id * of the TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to the TSG struct. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to the TSG struct. * * Disable h/w runlist scheduler for #nvgpu_tsg.runlist_id. */ @@ -524,9 +524,9 @@ void nvgpu_tsg_disable_sched(struct gk20a *g, struct nvgpu_tsg *tsg); /** * @brief Allocate zero initialized memory to store SM errors. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to the TSG struct. - * @param num_sm[in] Total number of SMs supported by h/w. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to the TSG struct. + * @param num_sm [in] Total number of SMs supported by h/w. * * Allocate zero initialized memory to store SM errors for all the SMs * supported by h/w. @@ -571,9 +571,9 @@ gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node) /** * @brief Set error notifier for all the channels bound to a TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. - * @param error_notifier[in] Error notifier defined by s/w. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. + * @param error_notifier [in] Error notifier defined by s/w. * * Set error notifier for all the channels bound to the tsg. * See include/nvgpu/error_notifier.h. @@ -589,9 +589,9 @@ void nvgpu_tsg_set_ctxsw_timeout_accumulated_ms(struct nvgpu_tsg *tsg, u32 ms); /** * @brief Abort all the channels bound to the TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. - * @param preempt[in] Flag to ask for preempting TSG. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. + * @param preempt [in] Flag to ask for preempting TSG. * * - Disable all the channels bound to the #tsg so that h/w does not schedule * them. @@ -608,10 +608,10 @@ void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt); * @brief Clear h/w bits PBDMA_FAULTED and ENG_FAULTED in CCSR channel h/w * register for all the channels bound to the TSG. * - * @param g[in] The GPU driver struct. - * @param tsg[in] Pointer to TSG struct. - * @param eng[in] Flag to ask for clearing ENG_FAULTED h/w bit. - * @param pbdma[in] Flag to ask for clearing PBDMA_FAULTED h/w bit. + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. + * @param eng [in] Flag to ask for clearing ENG_FAULTED h/w bit. + * @param pbdma [in] Flag to ask for clearing PBDMA_FAULTED h/w bit. * * If chip supports the h/w bits PBDMA_FAULTED and ENG_FAULTED and tsg * is non-NULL, clear PBDMA_FAULTED bit in CCSR channel h/w register if #pbdma