diff --git a/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c b/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
index 5316783dc..1edfda516 100644
--- a/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
@@ -378,7 +378,7 @@ int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 	int err;
 	struct nvgpu_bitmap_allocator *a;
 
-	if (WARN_ON(blk_size & (blk_size - 1))) {
+	if (WARN_ON(blk_size & (blk_size - 1U))) {
 		return -EINVAL;
 	}
 
@@ -386,12 +386,12 @@ int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 	 * blk_size must be a power-of-2; base length also need to be aligned
 	 * to blk_size.
 	 */
-	if (blk_size & (blk_size - 1) ||
-	    base & (blk_size - 1) || length & (blk_size - 1)) {
+	if (blk_size & (blk_size - 1U) ||
+	    base & (blk_size - 1U) || length & (blk_size - 1U)) {
 		return -EINVAL;
 	}
 
-	if (base == 0) {
+	if (base == 0U) {
 		base = blk_size;
 		length -= blk_size;
 	}
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
index e684e637d..a9f900695 100644
--- a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
@@ -74,7 +74,7 @@ static void balloc_compute_max_order(struct nvgpu_buddy_allocator *a)
 {
 	u64 true_max_order = ilog2(a->blks);
 
-	if (a->max_order == 0) {
+	if (a->max_order == 0U) {
 		a->max_order = true_max_order;
 		return;
 	}
@@ -95,7 +95,7 @@ static void balloc_allocator_align(struct nvgpu_buddy_allocator *a)
 {
 	a->start = ALIGN(a->base, a->blk_size);
 	WARN_ON(a->start != a->base);
-	a->end   = (a->base + a->length) & ~(a->blk_size - 1);
+	a->end   = (a->base + a->length) & ~(a->blk_size - 1U);
 	a->count = a->end - a->start;
 	a->blks  = a->count >> a->blk_shift;
 }
@@ -119,7 +119,7 @@ static struct nvgpu_buddy *balloc_new_buddy(struct nvgpu_buddy_allocator *a,
 	new_buddy->parent = parent;
 	new_buddy->start = start;
 	new_buddy->order = order;
-	new_buddy->end = start + (1 << order) * a->blk_size;
+	new_buddy->end = start + (U64(1) << order) * a->blk_size;
 	new_buddy->pte_size = BALLOC_PTE_SIZE_ANY;
 
 	return new_buddy;
@@ -185,7 +185,7 @@ static void balloc_blist_rem(struct nvgpu_buddy_allocator *a,
 
 static u64 balloc_get_order(struct nvgpu_buddy_allocator *a, u64 len)
 {
-	if (len == 0) {
+	if (len == 0U) {
 		return 0;
 	}
 
@@ -200,7 +200,7 @@ static u64 __balloc_max_order_in(struct nvgpu_buddy_allocator *a,
 {
 	u64 size = (end - start) >> a->blk_shift;
 
-	if (size > 0) {
+	if (size > 0U) {
 		return min_t(u64, ilog2(size), a->max_order);
 	} else {
 		return GPU_BALLOC_MAX_ORDER;
@@ -212,7 +212,7 @@ static u64 __balloc_max_order_in(struct nvgpu_buddy_allocator *a,
  */
 static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
 {
-	int i;
+	u32 i;
 	u64 bstart, bend, order;
 	struct nvgpu_buddy *buddy;
 
@@ -220,7 +220,7 @@ static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
 	bend = a->end;
 
 	/* First make sure the LLs are valid. */
-	for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+	for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
 		nvgpu_init_list_node(balloc_get_order_list(a, i));
 	}
 
@@ -239,7 +239,7 @@ static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
 	return 0;
 
 cleanup:
-	for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+	for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
 		if (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
 			buddy = nvgpu_list_first_entry(
 					balloc_get_order_list(a, i),
@@ -257,7 +257,7 @@ cleanup:
  */
 static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
 {
-	int i;
+	u32 i;
 	struct nvgpu_rbtree_node *node = NULL;
 	struct nvgpu_buddy *bud;
 	struct nvgpu_fixed_alloc *falloc;
@@ -299,8 +299,8 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
 	/*
 	 * Now clean up the unallocated buddies.
 	 */
-	for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
-		BUG_ON(a->buddy_list_alloced[i] != 0);
+	for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+		BUG_ON(a->buddy_list_alloced[i] != 0U);
 
 		while (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
 			bud = nvgpu_list_first_entry(
@@ -310,19 +310,19 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
 			nvgpu_kmem_cache_free(a->buddy_cache, bud);
 		}
 
-		if (a->buddy_list_len[i] != 0) {
+		if (a->buddy_list_len[i] != 0U) {
 			nvgpu_info(na->g,
 					"Excess buddies!!! (%d: %llu)",
 				i, a->buddy_list_len[i]);
 			BUG();
 		}
-		if (a->buddy_list_split[i] != 0) {
+		if (a->buddy_list_split[i] != 0U) {
 			nvgpu_info(na->g,
 					"Excess split nodes!!! (%d: %llu)",
 				i, a->buddy_list_split[i]);
 			BUG();
 		}
-		if (a->buddy_list_alloced[i] != 0) {
+		if (a->buddy_list_alloced[i] != 0U) {
 			nvgpu_info(na->g,
 					"Excess alloced nodes!!! (%d: %llu)",
 				i, a->buddy_list_alloced[i]);
@@ -392,14 +392,14 @@ static int balloc_split_buddy(struct nvgpu_buddy_allocator *a,
 	struct nvgpu_buddy *left, *right;
 	u64 half;
 
-	left = balloc_new_buddy(a, b, b->start, b->order - 1);
+	left = balloc_new_buddy(a, b, b->start, b->order - 1U);
 	if (!left) {
 		return -ENOMEM;
 	}
 
-	half = (b->end - b->start) / 2;
+	half = (b->end - b->start) / 2U;
 
-	right = balloc_new_buddy(a, b, b->start + half, b->order - 1);
+	right = balloc_new_buddy(a, b, b->start + half, b->order - 1U);
 	if (!right) {
 		nvgpu_kmem_cache_free(a->buddy_cache, left);
 		return -ENOMEM;
@@ -624,7 +624,7 @@ static void __balloc_get_parent_range(struct nvgpu_buddy_allocator *a,
 	u64 shifted_base = balloc_base_shift(a, base);
 
 	order++;
-	base_mask = ~((a->blk_size << order) - 1);
+	base_mask = ~((a->blk_size << order) - 1U);
 
 	shifted_base &= base_mask;
 
@@ -720,7 +720,7 @@ static u64 __balloc_do_alloc_fixed(struct nvgpu_buddy_allocator *a,
 	u64 align_order;
 
 	shifted_base = balloc_base_shift(a, base);
-	if (shifted_base == 0) {
+	if (shifted_base == 0U) {
 		align_order = __fls(len >> a->blk_shift);
 	} else {
 		align_order = min_t(u64,
@@ -871,11 +871,11 @@ static u64 __nvgpu_balloc_fixed_buddy(struct nvgpu_allocator *na,
 	struct nvgpu_buddy_allocator *a = na->priv;
 
 	/* If base isn't aligned to an order 0 block, fail. */
-	if (base & (a->blk_size - 1)) {
+	if (base & (a->blk_size - 1U)) {
 		goto fail;
 	}
 
-	if (len == 0) {
+	if (len == 0U) {
 		goto fail;
 	}
 
@@ -1255,10 +1255,10 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 	struct nvgpu_buddy_allocator *a;
 
 	/* blk_size must be greater than 0 and a power of 2. */
-	if (blk_size == 0) {
+	if (blk_size == 0U) {
 		return -EINVAL;
 	}
-	if (blk_size & (blk_size - 1)) {
+	if (blk_size & (blk_size - 1U)) {
 		return -EINVAL;
 	}
 
@@ -1291,7 +1291,7 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 	 * If base is 0 then modfy base to be the size of one block so that we
 	 * can return errors by returning addr == 0.
 	 */
-	if (a->base == 0) {
+	if (a->base == 0U) {
 		a->base = a->blk_size;
 		a->length -= a->blk_size;
 	}
@@ -1308,8 +1308,8 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 	 * requirement is not necessary.
 	 */
 	if (flags & GPU_ALLOC_GVA_SPACE && vm->big_pages &&
-	    (base & ((vm->big_page_size << 10) - 1) ||
-	     size & ((vm->big_page_size << 10) - 1))) {
+	    (base & ((vm->big_page_size << 10) - 1U) ||
+	     size & ((vm->big_page_size << 10) - 1U))) {
 		return -EINVAL;
 	}
 
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
index c9e332a59..fe3926b99 100644
--- a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
+++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
@@ -159,7 +159,7 @@ struct nvgpu_buddy_allocator {
 	/*
 	 * Impose an upper bound on the maximum order.
 	 */
-#define GPU_BALLOC_ORDER_LIST_LEN	(GPU_BALLOC_MAX_ORDER + 1)
+#define GPU_BALLOC_ORDER_LIST_LEN	(GPU_BALLOC_MAX_ORDER + 1U)
 
 	struct nvgpu_list_node buddy_list[GPU_BALLOC_ORDER_LIST_LEN];
 	u64 buddy_list_len[GPU_BALLOC_ORDER_LIST_LEN];
@@ -190,7 +190,7 @@ static inline struct nvgpu_buddy_allocator *buddy_allocator(
 }
 
 static inline struct nvgpu_list_node *balloc_get_order_list(
-	struct nvgpu_buddy_allocator *a, int order)
+	struct nvgpu_buddy_allocator *a, u64 order)
 {
 	return &a->buddy_list[order];
 }
diff --git a/drivers/gpu/nvgpu/common/mm/comptags.c b/drivers/gpu/nvgpu/common/mm/comptags.c
index 0926e78e7..e6c997028 100644
--- a/drivers/gpu/nvgpu/common/mm/comptags.c
+++ b/drivers/gpu/nvgpu/common/mm/comptags.c
@@ -37,7 +37,7 @@ int gk20a_comptaglines_alloc(struct gk20a_comptag_allocator *allocator,
 			0, len, 0);
 	if (addr < allocator->size) {
 		/* number zero is reserved; bitmap base is 1 */
-		*offset = 1 + addr;
+		*offset = 1U + addr;
 		bitmap_set(allocator->bitmap, addr, len);
 	} else {
 		err = -ENOMEM;
@@ -51,9 +51,9 @@ void gk20a_comptaglines_free(struct gk20a_comptag_allocator *allocator,
 			     u32 offset, u32 len)
 {
 	/* number zero is reserved; bitmap base is 1 */
-	u32 addr = offset - 1;
+	u32 addr = offset - 1U;
 
-	WARN_ON(offset == 0);
+	WARN_ON(offset == 0U);
 	WARN_ON(addr > allocator->size);
 	WARN_ON(addr + len > allocator->size);
 
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index 02273393a..47d1e8eec 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -98,7 +98,7 @@ static u64 __nvgpu_gmmu_map(struct vm_gk20a *vm,
 	 * therefor we should not try and free it. But otherwise, if we do
 	 * manage the VA alloc, we obviously must free it.
 	 */
-	if (addr != 0) {
+	if (addr != 0U) {
 		mem->free_gpu_va = false;
 	} else {
 		mem->free_gpu_va = true;
@@ -300,7 +300,7 @@ static int pd_allocate(struct vm_gk20a *vm,
 static u32 pd_index(const struct gk20a_mmu_level *l, u64 virt,
 		    struct nvgpu_gmmu_attrs *attrs)
 {
-	u64 pd_mask = (1ULL << ((u64)l->hi_bit[attrs->pgsz] + 1)) - 1ULL;
+	u64 pd_mask = (1ULL << ((u64)l->hi_bit[attrs->pgsz] + 1U)) - 1ULL;
 	u32 pd_shift = (u64)l->lo_bit[attrs->pgsz];
 
 	/*
@@ -399,7 +399,7 @@ static int __set_pd_level(struct vm_gk20a *vm,
 		 * start at a PDE boundary.
 		 */
 		chunk_size = min(length,
-				 pde_range - (virt_addr & (pde_range - 1)));
+				 pde_range - (virt_addr & (pde_range - 1U)));
 
 		/*
 		 * If the next level has an update_entry function then we know
@@ -573,7 +573,7 @@ static int __nvgpu_gmmu_do_update_page_table(struct vm_gk20a *vm,
 		virt_addr += chunk_length;
 		length    -= chunk_length;
 
-		if (length == 0) {
+		if (length == 0U) {
 			break;
 		}
 	}
@@ -615,7 +615,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
 
 	page_size = vm->gmmu_page_sizes[attrs->pgsz];
 
-	if (space_to_skip & (page_size - 1)) {
+	if (space_to_skip & (page_size - 1U)) {
 		return -EINVAL;
 	}
 
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 345b947d6..ab75b1365 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -205,15 +205,15 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
 
 u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
 {
-	WARN_ON(offset & 3);
+	WARN_ON(offset & 3U);
 	return nvgpu_mem_rd32(g, mem, offset / sizeof(u32));
 }
 
 void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
 		u32 offset, void *dest, u32 size)
 {
-	WARN_ON(offset & 3);
-	WARN_ON(size & 3);
+	WARN_ON(offset & 3U);
+	WARN_ON(size & 3U);
 
 	if (mem->aperture == APERTURE_SYSMEM) {
 		u8 *src = (u8 *)mem->cpu_va + offset;
@@ -246,15 +246,15 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
 
 void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
 {
-	WARN_ON(offset & 3);
+	WARN_ON(offset & 3U);
 	nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data);
 }
 
 void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 		void *src, u32 size)
 {
-	WARN_ON(offset & 3);
-	WARN_ON(size & 3);
+	WARN_ON(offset & 3U);
+	WARN_ON(size & 3U);
 
 	if (mem->aperture == APERTURE_SYSMEM) {
 		u8 *dest = (u8 *)mem->cpu_va + offset;
@@ -274,11 +274,11 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 		u32 c, u32 size)
 {
-	WARN_ON(offset & 3);
-	WARN_ON(size & 3);
-	WARN_ON(c & ~0xff);
+	WARN_ON(offset & 3U);
+	WARN_ON(size & 3U);
+	WARN_ON(c & ~0xffU);
 
-	c &= 0xff;
+	c &= 0xffU;
 
 	if (mem->aperture == APERTURE_SYSMEM) {
 		u8 *dest = (u8 *)mem->cpu_va + offset;
diff --git a/drivers/gpu/nvgpu/common/mm/page_allocator.c b/drivers/gpu/nvgpu/common/mm/page_allocator.c
index f6d704359..3225f170c 100644
--- a/drivers/gpu/nvgpu/common/mm/page_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/page_allocator.c
@@ -317,8 +317,8 @@ static void free_slab_page(struct nvgpu_page_allocator *a,
 	palloc_dbg(a, "Freeing slab page @ 0x%012llx", slab_page->page_addr);
 
 	BUG_ON((slab_page->state != SP_NONE && slab_page->state != SP_EMPTY) ||
-	       slab_page->nr_objects_alloced != 0 ||
-	       slab_page->bitmap != 0);
+	       slab_page->nr_objects_alloced != 0U ||
+	       slab_page->bitmap != 0U);
 
 	nvgpu_free(&a->source_allocator, slab_page->page_addr);
 	a->pages_freed++;
@@ -471,7 +471,7 @@ static void __nvgpu_free_slab(struct nvgpu_page_allocator *a,
 
 	slab_page->nr_objects_alloced--;
 
-	if (slab_page->nr_objects_alloced == 0) {
+	if (slab_page->nr_objects_alloced == 0U) {
 		new_state = SP_EMPTY;
 	} else {
 		new_state = SP_PARTIAL;
@@ -684,7 +684,7 @@ static u64 nvgpu_page_alloc(struct nvgpu_allocator *na, u64 len)
 
 	alloc_lock(na);
 	if (a->flags & GPU_ALLOC_4K_VIDMEM_PAGES &&
-	    real_len <= (a->page_size / 2)) {
+	    real_len <= (a->page_size / 2U)) {
 		alloc = __nvgpu_alloc_slab(a, real_len);
 	} else {
 		alloc = __nvgpu_alloc_pages(a, real_len);
@@ -698,7 +698,7 @@ static u64 nvgpu_page_alloc(struct nvgpu_allocator *na, u64 len)
 	__insert_page_alloc(a, alloc);
 
 	a->nr_allocs++;
-	if (real_len > a->page_size / 2) {
+	if (real_len > a->page_size / 2U) {
 		a->pages_alloced += alloc->length >> a->page_shift;
 	}
 	alloc_unlock(na);
diff --git a/drivers/gpu/nvgpu/common/mm/pd_cache.c b/drivers/gpu/nvgpu/common/mm/pd_cache.c
index db48d1686..335ef360b 100644
--- a/drivers/gpu/nvgpu/common/mm/pd_cache.c
+++ b/drivers/gpu/nvgpu/common/mm/pd_cache.c
@@ -76,20 +76,20 @@
 
 static u32 nvgpu_pd_cache_nr(u32 bytes)
 {
-	return ilog2(bytes >> (NVGPU_PD_CACHE_MIN_SHIFT - 1));
+	return ilog2(bytes >> (NVGPU_PD_CACHE_MIN_SHIFT - 1U));
 }
 
 static u32 nvgpu_pd_cache_get_mask(struct nvgpu_pd_mem_entry *pentry)
 {
 	u32 mask_offset = 1 << (PAGE_SIZE / pentry->pd_size);
 
-	return mask_offset - 1;
+	return mask_offset - 1U;
 }
 
 int nvgpu_pd_cache_init(struct gk20a *g)
 {
 	struct nvgpu_pd_cache *cache;
-	int i;
+	u32 i;
 
 	/*
 	 * This gets called from finalize_poweron() so we need to make sure we
@@ -105,7 +105,7 @@ int nvgpu_pd_cache_init(struct gk20a *g)
 		return -ENOMEM;
 	}
 
-	for (i = 0; i < NVGPU_PD_CACHE_COUNT; i++) {
+	for (i = 0U; i < NVGPU_PD_CACHE_COUNT; i++) {
 		nvgpu_init_list_node(&cache->full[i]);
 		nvgpu_init_list_node(&cache->partial[i]);
 	}
@@ -121,14 +121,14 @@ int nvgpu_pd_cache_init(struct gk20a *g)
 
 void nvgpu_pd_cache_fini(struct gk20a *g)
 {
-	int i;
+	u32 i;
 	struct nvgpu_pd_cache *cache = g->mm.pd_cache;
 
 	if (!cache) {
 		return;
 	}
 
-	for (i = 0; i < NVGPU_PD_CACHE_COUNT; i++) {
+	for (i = 0U; i < NVGPU_PD_CACHE_COUNT; i++) {
 		WARN_ON(!nvgpu_list_empty(&cache->full[i]));
 		WARN_ON(!nvgpu_list_empty(&cache->partial[i]));
 	}
@@ -305,7 +305,7 @@ static int nvgpu_pd_cache_alloc(struct gk20a *g, struct nvgpu_pd_cache *cache,
 
 	pd_dbg(g, "PD-Alloc [C] %u bytes", bytes);
 
-	if (bytes & (bytes - 1) ||
+	if (bytes & (bytes - 1U) ||
 	    (bytes >= PAGE_SIZE ||
 	     bytes < NVGPU_PD_CACHE_MIN)) {
 		pd_dbg(g, "PD-Alloc [C]   Invalid (bytes=%u)!", bytes);
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c
index e556be12e..b364f4d65 100644
--- a/drivers/gpu/nvgpu/common/mm/vm.c
+++ b/drivers/gpu/nvgpu/common/mm/vm.c
@@ -150,7 +150,7 @@ u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size, u32 pgsz_idx)
 	}
 
 	/* Be certain we round up to page_size if needed */
-	size = (size + ((u64)page_size - 1)) & ~((u64)page_size - 1);
+	size = (size + ((u64)page_size - 1U)) & ~((u64)page_size - 1U);
 
 	addr = nvgpu_alloc(vma, size);
 	if (!addr) {
@@ -202,7 +202,7 @@ void nvgpu_vm_mapping_batch_finish(struct vm_gk20a *vm,
  */
 int nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size)
 {
-	u64 mask = ((u64)vm->big_page_size << 10) - 1;
+	u64 mask = ((u64)vm->big_page_size << 10) - 1U;
 
 	if (base & mask || size & mask) {
 		return 0;
@@ -252,7 +252,7 @@ static int nvgpu_init_sema_pool(struct vm_gk20a *vm)
 	sema_sea->gpu_va = nvgpu_alloc_fixed(&vm->kernel,
 					     vm->va_limit -
 					     mm->channel.kernel_size,
-					     512 * PAGE_SIZE,
+					     512U * PAGE_SIZE,
 					     SZ_4K);
 	if (!sema_sea->gpu_va) {
 		nvgpu_free(&vm->kernel, sema_sea->gpu_va);
@@ -296,7 +296,7 @@ int __nvgpu_vm_init(struct mm_gk20a *mm,
 		return -ENOMEM;
 	}
 
-	if (WARN_ON(vm->guest_managed && kernel_reserved != 0)) {
+	if (WARN_ON(vm->guest_managed && kernel_reserved != 0U)) {
 		return -EINVAL;
 	}
 
@@ -387,7 +387,7 @@ int __nvgpu_vm_init(struct mm_gk20a *mm,
 	}
 
 	kernel_vma_flags = (kernel_reserved + low_hole) == aperture_size ?
-		0 : GPU_ALLOC_GVA_SPACE;
+		0U : GPU_ALLOC_GVA_SPACE;
 
 	/*
 	 * A "user" area only makes sense for the GVA spaces. For VMs where
@@ -967,7 +967,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
 						g, gk20a_cbc_op_clear,
 						comptags.offset,
 						(comptags.offset +
-						 comptags.lines - 1));
+						 comptags.lines - 1U));
 					gk20a_comptags_finish_clear(
 						os_buf, err == 0);
 					if (err) {
@@ -1036,7 +1036,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
 				      aperture);
 
 	if (clear_ctags) {
-		gk20a_comptags_finish_clear(os_buf, map_addr != 0);
+		gk20a_comptags_finish_clear(os_buf, map_addr != 0U);
 	}
 
 	if (!map_addr) {
diff --git a/drivers/gpu/nvgpu/common/mm/vm_area.c b/drivers/gpu/nvgpu/common/mm/vm_area.c
index 7e2b5c340..c2c0d569b 100644
--- a/drivers/gpu/nvgpu/common/mm/vm_area.c
+++ b/drivers/gpu/nvgpu/common/mm/vm_area.c
@@ -57,7 +57,7 @@ int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm,
 		return -EINVAL;
 	}
 
-	if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1)) {
+	if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1U)) {
 		nvgpu_err(g, "map offset must be buffer page size aligned 0x%llx",
 			  map_addr);
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c
index 0760a6cda..fc82c2e95 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios.c
+++ b/drivers/gpu/nvgpu/common/vbios/bios.c
@@ -26,15 +26,15 @@
 
 #include "gk20a/gk20a.h"
 
-#define BIT_HEADER_ID 0xb8ff
-#define BIT_HEADER_SIGNATURE 0x00544942
-#define PCI_EXP_ROM_SIG 0xaa55
-#define PCI_EXP_ROM_SIG_NV 0x4e56
+#define BIT_HEADER_ID 				0xb8ffU
+#define BIT_HEADER_SIGNATURE 			0x00544942U
+#define PCI_EXP_ROM_SIG 			0xaa55U
+#define PCI_EXP_ROM_SIG_NV 			0x4e56U
 
-#define INIT_DONE 0x71
-#define INIT_RESUME 0x72
-#define INIT_CONDITION 0x75
-#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
+#define INIT_DONE 				0x71U
+#define INIT_RESUME 				0x72U
+#define INIT_CONDITION 				0x75U
+#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 		0x8fU
 
 struct condition_entry {
 	u32 cond_addr;
@@ -67,18 +67,18 @@ struct bit {
 	u8 header_checksum;
 } __packed;
 
-#define TOKEN_ID_BIOSDATA 0x42
-#define TOKEN_ID_NVINIT_PTRS 0x49
-#define TOKEN_ID_FALCON_DATA 0x70
-#define TOKEN_ID_PERF_PTRS 0x50
-#define TOKEN_ID_CLOCK_PTRS 0x43
-#define TOKEN_ID_VIRT_PTRS 0x56
-#define TOKEN_ID_MEMORY_PTRS 0x4D
+#define TOKEN_ID_BIOSDATA 			0x42U
+#define TOKEN_ID_NVINIT_PTRS 			0x49U
+#define TOKEN_ID_FALCON_DATA 			0x70U
+#define TOKEN_ID_PERF_PTRS 			0x50U
+#define TOKEN_ID_CLOCK_PTRS 			0x43U
+#define TOKEN_ID_VIRT_PTRS 			0x56U
+#define TOKEN_ID_MEMORY_PTRS 			0x4DU
 
-#define NVLINK_CONFIG_DATA_HDR_VER_10 0x1
-#define NVLINK_CONFIG_DATA_HDR_10_SIZE 16
-#define NVLINK_CONFIG_DATA_HDR_11_SIZE 17
-#define NVLINK_CONFIG_DATA_HDR_12_SIZE 21
+#define NVLINK_CONFIG_DATA_HDR_VER_10 		0x1U
+#define NVLINK_CONFIG_DATA_HDR_10_SIZE 		16U
+#define NVLINK_CONFIG_DATA_HDR_11_SIZE 		17U
+#define NVLINK_CONFIG_DATA_HDR_12_SIZE 		21U
 
 struct nvlink_config_data_hdr_v1 {
 	u8 version;
@@ -91,8 +91,8 @@ struct nvlink_config_data_hdr_v1 {
 	u32 ac_coupling_mask;
 } __packed;
 
-#define MEMORY_PTRS_V1 1
-#define MEMORY_PTRS_V2 2
+#define MEMORY_PTRS_V1 				1U
+#define MEMORY_PTRS_V2 				2U
 
 struct memory_ptrs_v1 {
 	u8 rsvd0[2];
@@ -155,11 +155,11 @@ struct falcon_ucode_table_entry_v1 {
 	u32 desc_ptr;
 } __packed;
 
-#define TARGET_ID_PMU 0x01
-#define APPLICATION_ID_DEVINIT 0x04
-#define APPLICATION_ID_PRE_OS 0x01
+#define TARGET_ID_PMU 				0x01U
+#define APPLICATION_ID_DEVINIT 			0x04U
+#define APPLICATION_ID_PRE_OS 			0x01U
 
-#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1
+#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 	0x1U
 #define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr)           \
 	((hdr.v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \
 	FALCON_UCODE_FLAGS_VERSION_AVAILABLE)
@@ -170,10 +170,10 @@ struct falcon_ucode_table_entry_v1 {
  */
 
 #define FALCON_UCODE_GET_VERSION(hdr) \
-	((hdr.v2.v_desc >> 8) & 0xff)
+	((hdr.v2.v_desc >> 8) & 0xffU)
 
 #define FALCON_UCODE_GET_DESC_SIZE(hdr) \
-	((hdr.v2.v_desc >> 16) & 0xffff)
+	((hdr.v2.v_desc >> 16) & 0xffffU)
 
 struct falcon_ucode_desc_v1 {
 	union {
@@ -228,7 +228,7 @@ struct application_interface_entry_v1 {
 	u32 dmem_offset;
 } __packed;
 
-#define APPINFO_ID_DEVINIT 0x01
+#define APPINFO_ID_DEVINIT 			0x01U
 
 struct devinit_engine_interface {
 	u16 version;
@@ -316,7 +316,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 				pci_data->last_image,
 				pci_data->max_runtime_image_len);
 
-		if (pci_data->code_type == 0x3) {
+		if (pci_data->code_type == 0x3U) {
 			pci_ext_data = (struct pci_ext_data_struct *)
 				&g->bios.data[(offset +
 					       pci_rom->pci_data_struct_ptr +
@@ -332,9 +332,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 					pci_ext_data->flags);
 
 			nvgpu_log_fn(g, "expansion rom offset %x",
-					pci_data->image_len * 512);
+					pci_data->image_len * 512U);
 			g->bios.expansion_rom_offset =
-				pci_data->image_len * 512;
+				(u32)pci_data->image_len * 512U;
 			offset += pci_ext_data->sub_image_len * 512;
 			last = pci_ext_data->priv_last_image;
 		} else {
@@ -344,9 +344,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 	}
 
 	nvgpu_log_info(g, "read bios");
-	for (i = 0; i < g->bios.size - 6; i++) {
+	for (i = 0; i < g->bios.size - 6U; i++) {
 		if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID &&
-		    nvgpu_bios_rdu32(g, i+2) ==  BIT_HEADER_SIGNATURE) {
+		    nvgpu_bios_rdu32(g, i+2U) ==  BIT_HEADER_SIGNATURE) {
 			nvgpu_bios_parse_bit(g, i);
 			found = true;
 		}
@@ -394,7 +394,7 @@ u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
 {
 	struct nvlink_config_data_hdr_v1 config;
 
-	if (g->bios.nvlink_config_data_offset == 0) {
+	if (g->bios.nvlink_config_data_offset == 0U) {
 		return -EINVAL;
 	}
 
@@ -460,7 +460,7 @@ static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
 			interface.script_phys_base,
 			interface.script_size);
 
-	if (interface.version != 1) {
+	if (interface.version != 1U) {
 		return;
 	}
 	g->bios.devinit_tables_phys_base = interface.tables_phys_base;
@@ -478,7 +478,7 @@ static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset)
 			hdr.version, hdr.header_size,
 			hdr.entry_size, hdr.entry_count);
 
-	if (hdr.version != 1) {
+	if (hdr.version != 1U) {
 		return 0;
 	}
 
@@ -588,7 +588,7 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
 			hdr.entry_size, hdr.entry_count,
 			hdr.desc_version, hdr.desc_size);
 
-	if (hdr.version != 1) {
+	if (hdr.version != 1U) {
 		return -EINVAL;
 	}
 
@@ -697,9 +697,9 @@ void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
 					(table_id * data_size)),
 					perf_table_id_offset);
 
-		if (perf_table_id_offset != 0) {
+		if (perf_table_id_offset != 0U) {
 			/* check is perf_table_id_offset is > 64k */
-			if (perf_table_id_offset & ~0xFFFF) {
+			if (perf_table_id_offset & ~0xFFFFU) {
 				perf_table_ptr =
 					&g->bios.data[g->bios.expansion_rom_offset +
 						perf_table_id_offset];
@@ -747,7 +747,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, int offset)
 			nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
 			break;
 		case TOKEN_ID_FALCON_DATA:
-			if (bit_token.data_version == 2) {
+			if (bit_token.data_version == 2U) {
 				nvgpu_bios_parse_falcon_data_v2(g,
 						bit_token.data_ptr);
 			}
@@ -790,7 +790,7 @@ s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
 {
 	u32 val;
 	val = __nvgpu_bios_readbyte(g, offset);
-	val = val & 0x80 ? (val | ~0xff) : val;
+	val = val & 0x80U ? (val | ~0xffU) : val;
 
 	return (s8) val;
 }
@@ -800,7 +800,7 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
 	u16 val;
 
 	val = __nvgpu_bios_readbyte(g, offset) |
-		(__nvgpu_bios_readbyte(g, offset+1) << 8);
+		(__nvgpu_bios_readbyte(g, offset+1U) << 8U);
 
 	return val;
 }
@@ -810,9 +810,9 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
 	u32 val;
 
 	val = __nvgpu_bios_readbyte(g, offset) |
-		(__nvgpu_bios_readbyte(g, offset+1) << 8) |
-		(__nvgpu_bios_readbyte(g, offset+2) << 16) |
-		(__nvgpu_bios_readbyte(g, offset+3) << 24);
+		(__nvgpu_bios_readbyte(g, offset+1U) << 8U) |
+		(__nvgpu_bios_readbyte(g, offset+2U) << 16U) |
+		(__nvgpu_bios_readbyte(g, offset+3U) << 24U);
 
 	return val;
 }
@@ -825,7 +825,7 @@ static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condi
 
 	if (*condition) {
 
-		strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
+		strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xfU;
 
 		index = g->bios.mem_strap_xlat_tbl_ptr ?
 			nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
@@ -849,9 +849,9 @@ static void gp106_init_condition(struct gk20a *g, bool *condition,
 	entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
 		sizeof(entry)*condition_id);
 	entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
-		sizeof(entry)*condition_id + 4);
+		sizeof(entry)*condition_id + 4U);
 	entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
-		sizeof(entry)*condition_id + 8);
+		sizeof(entry)*condition_id + 8U);
 
 	if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
 		!= entry.cond_compare) {
@@ -879,9 +879,9 @@ int nvgpu_bios_execute_script(struct gk20a *g, u32 offset)
 
 		case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
 			operand[0] = nvgpu_bios_read_u32(g, ip);
-			operand[1] = nvgpu_bios_read_u8(g, ip+4);
-			operand[2] = nvgpu_bios_read_u8(g, ip+5);
-			ip += 6;
+			operand[1] = nvgpu_bios_read_u8(g, ip+4U);
+			operand[2] = nvgpu_bios_read_u8(g, ip+5U);
+			ip += 6U;
 
 			nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition,
 				operand[0], operand[1], operand[2], ip);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/allocator.h b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
index a38e8d518..698aafb39 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/allocator.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
@@ -186,11 +186,11 @@ nvgpu_alloc_carveout_from_co_entry(struct nvgpu_list_node *node)
  *     pointing to the allocation base (requires GPU_ALLOC_FORCE_CONTIG to be
  *     set as well).
  */
-#define GPU_ALLOC_GVA_SPACE		0x1
-#define GPU_ALLOC_NO_ALLOC_PAGE		0x2
-#define GPU_ALLOC_4K_VIDMEM_PAGES	0x4
-#define GPU_ALLOC_FORCE_CONTIG		0x8
-#define GPU_ALLOC_NO_SCATTER_GATHER	0x10
+#define GPU_ALLOC_GVA_SPACE		BIT(0)
+#define GPU_ALLOC_NO_ALLOC_PAGE		BIT(1)
+#define GPU_ALLOC_4K_VIDMEM_PAGES	BIT(2)
+#define GPU_ALLOC_FORCE_CONTIG		BIT(3)
+#define GPU_ALLOC_NO_SCATTER_GATHER	BIT(4)
 
 static inline void alloc_lock(struct nvgpu_allocator *a)
 {
@@ -236,7 +236,7 @@ int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 				  const char *name, u64 base, u64 length,
 				  u64 struct_size, u64 flags);
 
-#define GPU_BALLOC_MAX_ORDER		31
+#define GPU_BALLOC_MAX_ORDER		31U
 
 /*
  * Allocator APIs.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
index a83b0dd83..e58f5498f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
@@ -54,9 +54,9 @@ enum gk20a_mem_rw_flag {
  * structure is of course depending on this. The MIN_SHIFT define is the right
  * number of bits to shift to determine which list to use in the array of lists.
  */
-#define NVGPU_PD_CACHE_MIN		256
-#define NVGPU_PD_CACHE_MIN_SHIFT	9
-#define NVGPU_PD_CACHE_COUNT		4
+#define NVGPU_PD_CACHE_MIN		256U
+#define NVGPU_PD_CACHE_MIN_SHIFT	9U
+#define NVGPU_PD_CACHE_COUNT		4U
 
 struct nvgpu_pd_mem_entry {
 	struct nvgpu_mem		mem;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
index 4b5259236..97686eec2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
@@ -72,7 +72,7 @@ typedef long long		s64;
 	})
 #define min3(a, b, c)			min(min(a, b), c)
 
-#define PAGE_SIZE	4096
+#define PAGE_SIZE	4096U
 
 #define ARRAY_SIZE(array)			\
 	(sizeof(array) / sizeof((array)[0]))
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index ad8c7ccaf..b47d4ee0b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -207,12 +207,12 @@ struct vm_gk20a {
 /*
  * Mapping flags.
  */
-#define NVGPU_VM_MAP_FIXED_OFFSET			(1 << 0)
-#define NVGPU_VM_MAP_CACHEABLE				(1 << 1)
-#define NVGPU_VM_MAP_IO_COHERENT			(1 << 2)
-#define NVGPU_VM_MAP_UNMAPPED_PTE			(1 << 3)
-#define NVGPU_VM_MAP_DIRECT_KIND_CTRL			(1 << 4)
-#define NVGPU_VM_MAP_L3_ALLOC				(1 << 5)
+#define NVGPU_VM_MAP_FIXED_OFFSET			BIT32(0)
+#define NVGPU_VM_MAP_CACHEABLE				BIT32(1)
+#define NVGPU_VM_MAP_IO_COHERENT			BIT32(2)
+#define NVGPU_VM_MAP_UNMAPPED_PTE			BIT32(3)
+#define NVGPU_VM_MAP_DIRECT_KIND_CTRL			BIT32(4)
+#define NVGPU_VM_MAP_L3_ALLOC				BIT32(5)
 
 #define NVGPU_KIND_INVALID				-1
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
index a055ada35..53e1cb85d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
@@ -60,8 +60,8 @@ nvgpu_vm_area_from_vm_area_list(struct nvgpu_list_node *node)
 /*
  * Alloc space flags.
  */
-#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET		(1 << 0)
-#define NVGPU_VM_AREA_ALLOC_SPARSE			(1 << 1)
+#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET		BIT(0)
+#define NVGPU_VM_AREA_ALLOC_SPARSE			BIT(1)
 
 int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
 			u64 *addr, u32 flags);