From 2fa0e6fca1a99e69a105a47193c35e81b418c7c2 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 15 Jan 2021 11:26:07 -0800 Subject: [PATCH] gpu: nvgpu: resolve misra 5.7 violation Rule 5.7 doesn't allow an identifier to be reused. This patch renames variable "ops" to resolve this violation. Jira NVGPU-6272 Change-Id: Ica8364a21d28dcf02d935a1b212e334b3f48c98a Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471047 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c index 077e1a22d..9e806ce8e 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c @@ -1,7 +1,7 @@ /* * GM20B Master Control * - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -58,7 +58,7 @@ u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) u32 gm20b_mc_isr_nonstall(struct gk20a *g) { - u32 ops = 0U; + u32 nonstall_ops = 0U; u32 mc_intr_1; u32 i; @@ -69,7 +69,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) } if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) { - ops |= g->ops.fifo.intr_1_isr(g); + nonstall_ops |= g->ops.fifo.intr_1_isr(g); } for (i = 0U; i < g->fifo.num_engines; i++) { @@ -81,19 +81,19 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) /* GR Engine */ if (nvgpu_device_is_graphics(g, dev)) { - ops |= g->ops.gr.intr.nonstall_isr(g); + nonstall_ops |= g->ops.gr.intr.nonstall_isr(g); } /* CE Engine */ if (nvgpu_device_is_ce(g, dev) && (g->ops.ce.isr_nonstall != NULL)) { - ops |= g->ops.ce.isr_nonstall(g, + nonstall_ops |= g->ops.ce.isr_nonstall(g, dev->inst_id, dev->pri_base); } } - return ops; + return nonstall_ops; } static int gm20b_mc_enable(struct gk20a *g, u32 mask, bool enable)