diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 8fdd7f33f..d99414ed6 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -598,7 +598,7 @@ static int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg, } if (g->ops.channel.clear != NULL) { - g->ops.channel.clear(ch); + g->ops.channel.clear(g, ch->runlist->id, ch->chid); } /* Channel should be seen as TSG channel while updating runlist */ @@ -743,7 +743,7 @@ fail_common: nvgpu_tsg_abort(g, tsg, true); if (g->ops.channel.clear != NULL) { - g->ops.channel.clear(ch); + g->ops.channel.clear(g, ch->runlist->id, ch->chid); } /* If channel unbind fails, channel is still part of runlist */ diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h index b77b2a60d..73463c155 100644 --- a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h +++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,6 +34,7 @@ void ga10b_channel_enable(struct nvgpu_channel *ch); void ga10b_channel_disable(struct nvgpu_channel *ch); void ga10b_channel_bind(struct nvgpu_channel *ch); void ga10b_channel_unbind(struct nvgpu_channel *ch); +void ga10b_channel_clear(struct gk20a *g, u32 runlist_id, u32 chid); void ga10b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *state); void ga10b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch, diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c index d233d7553..b0bc615c2 100644 --- a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -83,11 +83,8 @@ void ga10b_channel_disable(struct nvgpu_channel *ch) void ga10b_channel_bind(struct nvgpu_channel *ch) { struct gk20a *g = ch->g; - struct nvgpu_runlist *runlist = NULL; int err; - runlist = ch->runlist; - /* Enable subcontext */ if (g->ops.tsg.add_subctx_channel_hw != NULL) { err = g->ops.tsg.add_subctx_channel_hw(ch, ch->replayable); @@ -98,9 +95,7 @@ void ga10b_channel_bind(struct nvgpu_channel *ch) } /* Enable channel */ - nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid), - runlist_chram_channel_update_f( - runlist_chram_channel_update_enable_channel_v())); + g->ops.channel.enable(ch); nvgpu_atomic_set(&ch->bound, CHANNEL_BOUND); } @@ -149,13 +144,19 @@ void ga10b_channel_unbind(struct nvgpu_channel *ch) if (nvgpu_atomic_cmpxchg(&ch->bound, CHANNEL_BOUND, CHANNEL_UNBOUND) != 0) { - nvgpu_chram_bar0_writel(g, runlist, - runlist_chram_channel_r(ch->chid), - runlist_chram_channel_update_f( - runlist_chram_channel_update_clear_channel_v())); + g->ops.channel.clear(g, runlist->id, ch->chid); } } +void ga10b_channel_clear(struct gk20a *g, u32 runlist_id, u32 chid) +{ + nvgpu_chram_bar0_writel(g, + g->fifo.runlists[runlist_id], + runlist_chram_channel_r(chid), + runlist_chram_channel_update_f( + runlist_chram_channel_update_clear_channel_v())); +} + #define NUM_STATUS_STR 8U static u32 ga10b_channel_status_mask(void) diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 5632ceb53..1cbd364fb 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1197,7 +1197,7 @@ static const struct gops_channel ga100_ops_channel = { .free_inst = nvgpu_channel_free_inst, .bind = ga10b_channel_bind, .unbind = ga10b_channel_unbind, - .clear = ga10b_channel_unbind, + .clear = ga10b_channel_clear, .enable = ga10b_channel_enable, .disable = ga10b_channel_disable, .count = ga100_channel_count, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index a5715668f..fad88e4d8 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1213,7 +1213,7 @@ static const struct gops_channel ga10b_ops_channel = { .free_inst = nvgpu_channel_free_inst, .bind = ga10b_channel_bind, .unbind = ga10b_channel_unbind, - .clear = ga10b_channel_unbind, + .clear = ga10b_channel_clear, .enable = ga10b_channel_enable, .disable = ga10b_channel_disable, .count = ga10b_channel_count, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h index 07010879b..768569c04 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -141,7 +141,7 @@ struct gops_channel { void (*abort_clean_up)(struct nvgpu_channel *ch); void (*reset_faulted)(struct gk20a *g, struct nvgpu_channel *ch, bool eng, bool pbdma); - void (*clear)(struct nvgpu_channel *ch); + void (*clear)(struct gk20a *g, u32 runlist_id, u32 chid); int (*get_vmid)(struct nvgpu_channel *ch, u32 *vmid); #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT