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gpu: nvgpu: Move programming of host registers to fifo

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Move code that touches host registers to fifo HAL. This sorts out
some of the dependencies between fifo HAL and channel HAL.

Change-Id: I2bff0443ae1c1fa5608e620974b440696d1cfdc4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323385
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2017-03-17 15:40:34 -07:00
committed by mobile promotions
parent 9773dbf905
commit 3032acfc04
1 changed files with 6 additions and 4 deletions
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10
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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@@ -19,6 +19,7 @@
#include <nvgpu/timers.h>
#include "gk20a/gk20a.h"
#include "gk20a/fifo_gk20a.h"
#include "gp10b/fifo_gp10b.h"
@@ -105,7 +106,8 @@ static void gv11b_userd_writeback_config(struct gk20a *g)
}
static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
u64 gpfifo_base, u32 gpfifo_entries,
unsigned long acquire_timeout, u32 flags)
{
struct gk20a *g = c->g;
struct mem_desc *mem = &c->inst_block;
@@ -145,7 +147,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
pbdma_target_engine_sw_f());
gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
channel_gk20a_pbdma_acquire_val(c));
g->ops.fifo.pbdma_acquire_val(acquire_timeout));
gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
pbdma_runlist_timeslice_timeout_128_f() |
@@ -165,7 +167,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
gk20a_mem_wr32(g, mem, ram_fc_config_w(),
pbdma_config_auth_level_privileged_f());
gk20a_channel_setup_ramfc_for_privileged_channel(c);
gk20a_fifo_setup_ramfc_for_privileged_channel(c);
}
/* Enable userd writeback */
@@ -213,7 +215,7 @@ static void channel_gv11b_unbind(struct channel_gk20a *ch)
{
gk20a_dbg_fn("");
channel_gk20a_unbind(ch);
gk20a_fifo_channel_unbind(ch);
}
static u32 gv11b_fifo_get_num_fifos(struct gk20a *g)