nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: common: fix MISRA Rule 10.4 Violations

Browse Source 
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.

This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sai Nikhil
2018-10-08 15:30:37 +05:30
committed by mobile promotions
parent 2bded93b28
commit 303fc7496c
42 changed files with 149 additions and 149 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/bios.h
View File

@@ -27,8 +27,8 @@
struct gk20a;
#define PERF_PTRS_WIDTH 0x4
#define PERF_PTRS_WIDTH_16 0x2
#define PERF_PTRS_WIDTH U8(0x4)
#define PERF_PTRS_WIDTH_16 U8(0x2)
enum {
CLOCKS_TABLE = 2,