diff --git a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c
index 3b64adc42..3977029d0 100644
--- a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c
+++ b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c
@@ -198,6 +198,11 @@ int nvgpu_gsp_sched_bootstrap_ns(struct gk20a *g)
 		goto de_init;
 	}
 
+	/* setup gsp ctx instance */
+	if (g->ops.gsp.falcon_setup_boot_config != NULL) {
+		g->ops.gsp.falcon_setup_boot_config(g);
+	}
+
 	status = gsp_sched_wait_for_init(g, gsp_sched, GSP_WAIT_TIME_MS);
 	if (status != 0) {
 		nvgpu_err(g, "gsp wait for basic init failed ");
diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
index 49f8fe0bc..917498aaa 100644
--- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
@@ -470,25 +470,24 @@ int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
 
 void ga10b_gsp_flcn_setup_boot_config(struct gk20a *g)
 {
+	struct mm_gk20a *mm = &g->mm;
+	u32 inst_block_ptr;
+
 	nvgpu_log_fn(g, " ");
 
-	/* setup apertures - virtual */
-	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-			pgsp_fbif_transcfg_mem_type_physical_f() |
-			pgsp_fbif_transcfg_target_local_fb_f());
-	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-			pgsp_fbif_transcfg_mem_type_virtual_f());
-	/* setup apertures - physical */
-	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-			pgsp_fbif_transcfg_mem_type_physical_f() |
-			pgsp_fbif_transcfg_target_local_fb_f());
-	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-			pgsp_fbif_transcfg_mem_type_physical_f() |
-			pgsp_fbif_transcfg_target_coherent_sysmem_f());
-	gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-			pgsp_fbif_transcfg_mem_type_physical_f() |
-			pgsp_fbif_transcfg_target_noncoherent_sysmem_f());
+	/*
+	 * The instance block address to write is the lower 32-bits of the 4K-
+	 * aligned physical instance block address.
+	 */
+	inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->gsp.inst_block);
 
+	gk20a_writel(g, pgsp_falcon_nxtctx_r(),
+		pgsp_falcon_nxtctx_ctxptr_f(inst_block_ptr) |
+		pgsp_falcon_nxtctx_ctxvalid_f(1) |
+		nvgpu_aperture_mask(g, &mm->gsp.inst_block,
+			pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(),
+			pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(),
+			pgsp_falcon_nxtctx_ctxtgt_fb_f()));
 }
 
 int ga10b_gsp_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index 2fbd2c163..4f3a8d333 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1950,6 +1950,11 @@ int ga10b_init_hal(struct gk20a *g)
 		nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true);
 	}
 
+	/*
+	 * enable GSP VM for gsp scheduler firmware
+	 */
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true);
+
 	/*
 	 * ga10b bypasses the IOMMU since it uses a special nvlink path to
 	 * memory.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
index a535ab0fe..6e3e769e1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
@@ -172,4 +172,10 @@
 #define pgsp_falcon_ecc_status_uncorrected_err_emem_m()       (U32(0x1U) << 13U)
 #define pgsp_falcon_ecc_status_uncorrected_err_dcls_m()       (U32(0x1U) << 11U)
 #define pgsp_falcon_ecc_status_uncorrected_err_reg_m()        (U32(0x1U) << 12U)
+#define pgsp_falcon_nxtctx_r()                                     (0x00110054U)
+#define pgsp_falcon_nxtctx_ctxptr_f(v)             ((U32(v) & 0xfffffffU) << 0U)
+#define pgsp_falcon_nxtctx_ctxtgt_fb_f()                                  (0x0U)
+#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f()                      (0x20000000U)
+#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f()                     (0x30000000U)
+#define pgsp_falcon_nxtctx_ctxvalid_f(v)                ((U32(v) & 0x1U) << 30U)
 #endif