diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 0ed2fe67f..69855dd7a 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -399,9 +399,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ common/vgpu/ltc_vgpu.o \ common/vgpu/gr/gr_vgpu.o \ common/vgpu/gr/ctx_vgpu.o \ - common/vgpu/gr/vgpu_gr_gm20b.o \ - common/vgpu/gr/vgpu_gr_gp10b.o \ - common/vgpu/gr/vgpu_gr_gv11b.o \ common/vgpu/fifo/fifo_vgpu.o \ common/vgpu/fifo/runlist_vgpu.o \ common/vgpu/fifo/vgpu_fifo_gv11b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 86c74fe3b..902b00c6d 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -321,9 +321,6 @@ srcs += common/sim.c \ common/vgpu/mm_vgpu.c \ common/vgpu/gr/gr_vgpu.c \ common/vgpu/gr/ctx_vgpu.c \ - common/vgpu/gr/vgpu_gr_gv11b.c \ - common/vgpu/gr/vgpu_gr_gp10b.c \ - common/vgpu/gr/vgpu_gr_gm20b.c \ common/vgpu/clk_vgpu.c \ common/vgpu/debugger_vgpu.c \ common/vgpu/ltc_vgpu.c \ diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index a172e7050..1a2149035 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -53,8 +53,6 @@ #include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" #include "gp10b/gp10b.h" #include "gp10b/hal_gp10b.h" -#include "common/vgpu/gr/vgpu_gr_gm20b.h" -#include "common/vgpu/gr/vgpu_gr_gp10b.h" #include "vgpu_mm_gp10b.h" #include "vgpu_fuse_gp10b.h" @@ -141,11 +139,11 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_tpc_num = gr_gm20b_get_tpc_num, .detect_sm_arch = vgpu_gr_detect_sm_arch, .pagepool_default_size = gr_gp10b_pagepool_default_size, - .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, + .init_ctx_state = vgpu_gr_init_ctx_state, .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx, .free_gr_ctx = vgpu_gr_free_gr_ctx, .init_ctxsw_preemption_mode = - vgpu_gr_gp10b_init_ctxsw_preemption_mode, + vgpu_gr_init_ctxsw_preemption_mode, .update_ctxsw_preemption_mode = gr_gp10b_update_ctxsw_preemption_mode, .dump_gr_regs = NULL, @@ -157,7 +155,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_max_fbps_count = vgpu_gr_get_max_fbps_count, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .wait_empty = NULL, - .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, + .init_cyclestats = vgpu_gr_init_cyclestats, .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, .bpt_reg_info = NULL, .get_access_map = gr_gp10b_get_access_map, @@ -204,7 +202,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, .disable_rd_coalesce = NULL, .set_boosted_ctx = NULL, - .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, + .set_preemption_mode = vgpu_gr_set_preemption_mode, .set_czf_bypass = NULL, .init_czf_bypass = gr_gp10b_init_czf_bypass, .pre_process_sm_exception = NULL, @@ -213,7 +211,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .set_bes_crop_debug3 = NULL, .set_bes_crop_debug4 = NULL, .set_ctxsw_preemption_mode = - vgpu_gr_gp10b_set_ctxsw_preemption_mode, + vgpu_gr_set_ctxsw_preemption_mode, .init_gfxp_wfi_timeout_count = gr_gp10b_init_gfxp_wfi_timeout_count, .get_max_gfxp_wfi_timeout_count = @@ -230,6 +228,14 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .set_debug_mode = gm20b_gr_set_debug_mode, + .get_ctx_spill_size = gp10b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gp10b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gp10b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gp10b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index 865eb6bc9..67f79cd90 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -39,12 +39,16 @@ #include #include #include +#include #include #include "gr_vgpu.h" #include "ctx_vgpu.h" +#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" +#include "common/vgpu/gv11b/vgpu_subctx_gv11b.h" + void vgpu_gr_detect_sm_arch(struct gk20a *g) { struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -68,12 +72,26 @@ int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va) nvgpu_log_fn(g, " "); + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) { + err = vgpu_gv11b_alloc_subctx_header(c); + if (err) { + return err; + } + } + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX; msg.handle = vgpu_get_handle(c->g); p->handle = c->virt_ctx; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - return (err || msg.ret) ? -1 : 0; + if (err || msg.ret) { + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) { + vgpu_gv11b_free_subctx_header(c); + } + return -1; + } else { + return 0; + } } static int vgpu_gr_commit_global_ctx_buffers(struct gk20a *g, @@ -112,6 +130,13 @@ int vgpu_gr_init_ctx_state(struct gk20a *g) #ifdef CONFIG_GK20A_CTXSW_TRACE g->gr.ctx_vars.fecs_trace_buffer_size = nvgpu_gr_fecs_trace_buffer_size(g); #endif + + g->gr.ctx_vars.preempt_image_size = + priv->constants.preempt_ctx_size; + if (!g->gr.ctx_vars.preempt_image_size) { + return -EINVAL; + } + return 0; } @@ -127,15 +152,13 @@ int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) return -ENOMEM; } - size = gr->bundle_cb_default_size * - gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); + size = g->ops.gr.get_global_ctx_cb_buffer_size(g); nvgpu_log_info(g, "cb_buffer_size : %d", size); nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_CIRCULAR, size); - size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); + size = g->ops.gr.get_global_ctx_pagepool_buffer_size(g); nvgpu_log_info(g, "pagepool_buffer_size : %d", size); nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, @@ -1145,3 +1168,264 @@ int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable) return err ? err : msg.ret; } + +void vgpu_gr_init_cyclestats(struct gk20a *g) +{ +#if defined(CONFIG_GK20A_CYCLE_STATS) + bool snapshots_supported = true; + + /* cyclestats not supported on vgpu */ + nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false); + + g->gr.max_css_buffer_size = vgpu_css_get_buffer_size(g); + + /* snapshots not supported if the buffer size is 0 */ + if (g->gr.max_css_buffer_size == 0) { + snapshots_supported = false; + } + + nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, + snapshots_supported); +#endif +} + +int vgpu_gr_init_ctxsw_preemption_mode(struct gk20a *g, + struct nvgpu_gr_ctx *gr_ctx, + struct vm_gk20a *vm, + u32 class, + u32 flags) +{ + u32 graphics_preempt_mode = 0; + u32 compute_preempt_mode = 0; + struct vgpu_priv_data *priv = vgpu_get_priv_data(g); + int err; + + nvgpu_log_fn(g, " "); + + if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) { + graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; + } + if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) { + compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; + } + + if (priv->constants.force_preempt_mode && !graphics_preempt_mode && + !compute_preempt_mode) { + graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ? + NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0; + compute_preempt_mode = + g->ops.gr.is_valid_compute_class(g, class) ? + NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0; + } + + if (graphics_preempt_mode || compute_preempt_mode) { + if (g->ops.gr.set_ctxsw_preemption_mode) { + err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, + class, graphics_preempt_mode, compute_preempt_mode); + if (err) { + nvgpu_err(g, + "set_ctxsw_preemption_mode failed"); + return err; + } + } else { + return -ENOSYS; + } + } + + nvgpu_log_fn(g, "done"); + return 0; +} + +int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, + struct nvgpu_gr_ctx *gr_ctx, + struct vm_gk20a *vm, u32 class, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = + &msg.params.gr_bind_ctxsw_buffers; + int err = 0; + + if (g->ops.gr.is_valid_gfx_class(g, class) && + g->gr.ctx_vars.force_preemption_gfxp) { + graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; + } + + if (g->ops.gr.is_valid_compute_class(g, class) && + g->gr.ctx_vars.force_preemption_cilp) { + compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; + } + + /* check for invalid combinations */ + if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) { + return -EINVAL; + } + + if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && + (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) { + return -EINVAL; + } + + /* set preemption modes */ + switch (graphics_preempt_mode) { + case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: + { + u32 spill_size = g->ops.gr.get_ctx_spill_size(g); + u32 pagepool_size = g->ops.gr.get_ctx_pagepool_size(g); + u32 betacb_size = g->ops.gr.get_ctx_betacb_size(g); + u32 attrib_cb_size = + g->ops.gr.get_ctx_attrib_cb_size(g, betacb_size); + struct nvgpu_mem *desc; + + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + nvgpu_log_info(g, "gfxp context preempt size=%d", + g->gr.ctx_vars.preempt_image_size); + nvgpu_log_info(g, "gfxp context spill size=%d", spill_size); + nvgpu_log_info(g, "gfxp context pagepool size=%d", pagepool_size); + nvgpu_log_info(g, "gfxp context attrib cb size=%d", + attrib_cb_size); + + nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, + NVGPU_GR_CTX_PREEMPT_CTXSW, + g->gr.ctx_vars.preempt_image_size); + nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, + NVGPU_GR_CTX_SPILL_CTXSW, spill_size); + nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, + NVGPU_GR_CTX_BETACB_CTXSW, attrib_cb_size); + nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, + NVGPU_GR_CTX_PAGEPOOL_CTXSW, pagepool_size); + + err = nvgpu_gr_ctx_alloc_ctxsw_buffers(g, gr_ctx, + g->gr.gr_ctx_desc, vm); + if (err != 0) { + nvgpu_err(g, "cannot allocate ctxsw buffers"); + goto fail; + } + + desc = &gr_ctx->preempt_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; + + desc = &gr_ctx->spill_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; + + desc = &gr_ctx->pagepool_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; + + desc = &gr_ctx->betacb_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; + + gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; + break; + } + case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: + gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + break; + + default: + break; + } + + if (g->ops.gr.is_valid_compute_class(g, class)) { + switch (compute_preempt_mode) { + case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: + gr_ctx->compute_preempt_mode = + NVGPU_PREEMPTION_MODE_COMPUTE_WFI; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; + break; + case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: + gr_ctx->compute_preempt_mode = + NVGPU_PREEMPTION_MODE_COMPUTE_CTA; + p->mode = + TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; + break; + case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: + gr_ctx->compute_preempt_mode = + NVGPU_PREEMPTION_MODE_COMPUTE_CILP; + p->mode = + TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; + break; + default: + break; + } + } + + if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { + msg.cmd = TEGRA_VGPU_CMD_BIND_GR_CTXSW_BUFFERS; + msg.handle = vgpu_get_handle(g); + p->tsg_id = gr_ctx->tsgid; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) { + err = -ENOMEM; + goto fail; + } + } + + return err; + +fail: + nvgpu_err(g, "%s failed %d", __func__, err); + return err; +} + +int vgpu_gr_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + struct nvgpu_gr_ctx *gr_ctx; + struct gk20a *g = ch->g; + struct tsg_gk20a *tsg; + struct vm_gk20a *vm; + u32 class; + int err; + + class = ch->obj_class; + if (!class) { + return -EINVAL; + } + + tsg = tsg_gk20a_from_ch(ch); + if (!tsg) { + return -EINVAL; + } + + vm = tsg->vm; + gr_ctx = tsg->gr_ctx; + + /* skip setting anything if both modes are already set */ + if (graphics_preempt_mode && + (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { + graphics_preempt_mode = 0; + } + + if (compute_preempt_mode && + (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { + compute_preempt_mode = 0; + } + + if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) { + return 0; + } + + if (g->ops.gr.set_ctxsw_preemption_mode) { + err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class, + graphics_preempt_mode, + compute_preempt_mode); + if (err) { + nvgpu_err(g, "set_ctxsw_preemption_mode failed"); + return err; + } + } else { + err = -ENOSYS; + } + + return err; +} diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h index 9c5b6f38e..de08d3b73 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h @@ -34,6 +34,8 @@ struct nvgpu_gr_zbc_entry; struct nvgpu_gr_zbc_query_params; struct dbg_session_gk20a; struct tsg_gk20a; +struct vm_gk20a; +struct nvgpu_gr_ctx; void vgpu_gr_detect_sm_arch(struct gk20a *g); int vgpu_gr_init_ctx_state(struct gk20a *g); @@ -75,4 +77,19 @@ int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); int vgpu_gr_init_sm_id_table(struct gk20a *g); int vgpu_gr_init_fs_state(struct gk20a *g); int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable); +void vgpu_gr_init_cyclestats(struct gk20a *g); +int vgpu_gr_init_ctxsw_preemption_mode(struct gk20a *g, + struct nvgpu_gr_ctx *gr_ctx, + struct vm_gk20a *vm, + u32 class, + u32 flags); +int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, + struct nvgpu_gr_ctx *gr_ctx, + struct vm_gk20a *vm, u32 class, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); +int vgpu_gr_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode); + #endif /* NVGPU_GR_VGPU_H */ diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.c deleted file mode 100644 index d22854055..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" -#include "vgpu_gr_gm20b.h" - -void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g) -{ -#if defined(CONFIG_GK20A_CYCLE_STATS) - bool snapshots_supported = true; - - /* cyclestats not supported on vgpu */ - nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false); - - g->gr.max_css_buffer_size = vgpu_css_get_buffer_size(g); - - /* snapshots not supported if the buffer size is 0 */ - if (g->gr.max_css_buffer_size == 0) { - snapshots_supported = false; - } - - nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, - snapshots_supported); -#endif -} diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.h deleted file mode 100644 index 1c6b475e5..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gm20b.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VGPU_GR_GM20B_H -#define NVGPU_VGPU_GR_GM20B_H - -struct gk20a; - -void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g); - -#endif /* NVGPU_VGPU_GR_GM20B_H */ diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.c deleted file mode 100644 index 594ff7840..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ctx_vgpu.h" -#include "vgpu_gr_gm20b.h" -#include "vgpu_gr_gp10b.h" - -#include "gp10b/gr_gp10b.h" - -#include - -int vgpu_gr_gp10b_init_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, - u32 class, - u32 flags) -{ - u32 graphics_preempt_mode = 0; - u32 compute_preempt_mode = 0; - struct vgpu_priv_data *priv = vgpu_get_priv_data(g); - int err; - - nvgpu_log_fn(g, " "); - - if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) { - graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; - } - if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) { - compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; - } - - if (priv->constants.force_preempt_mode && !graphics_preempt_mode && - !compute_preempt_mode) { - graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ? - NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0; - compute_preempt_mode = - g->ops.gr.is_valid_compute_class(g, class) ? - NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0; - } - - if (graphics_preempt_mode || compute_preempt_mode) { - if (g->ops.gr.set_ctxsw_preemption_mode) { - err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, - class, graphics_preempt_mode, compute_preempt_mode); - if (err) { - nvgpu_err(g, - "set_ctxsw_preemption_mode failed"); - return err; - } - } else { - return -ENOSYS; - } - } - - nvgpu_log_fn(g, "done"); - return 0; -} - -int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, u32 class, - u32 graphics_preempt_mode, - u32 compute_preempt_mode) -{ - struct tegra_vgpu_cmd_msg msg = {}; - struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = - &msg.params.gr_bind_ctxsw_buffers; - int err = 0; - - if (g->ops.gr.is_valid_gfx_class(g, class) && - g->gr.ctx_vars.force_preemption_gfxp) { - graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; - } - - if (g->ops.gr.is_valid_compute_class(g, class) && - g->gr.ctx_vars.force_preemption_cilp) { - compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; - } - - /* check for invalid combinations */ - if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) { - return -EINVAL; - } - - if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && - (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) { - return -EINVAL; - } - - /* set preemption modes */ - switch (graphics_preempt_mode) { - case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: - { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - nvgpu_gr_config_get_max_tpc_count(g->gr.config); - struct nvgpu_mem *desc; - - attrib_cb_size = ALIGN(attrib_cb_size, 128); - - nvgpu_log_info(g, "gfxp context preempt size=%d", - g->gr.ctx_vars.preempt_image_size); - nvgpu_log_info(g, "gfxp context spill size=%d", spill_size); - nvgpu_log_info(g, "gfxp context pagepool size=%d", pagepool_size); - nvgpu_log_info(g, "gfxp context attrib cb size=%d", - attrib_cb_size); - - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_PREEMPT_CTXSW, - g->gr.ctx_vars.preempt_image_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_SPILL_CTXSW, spill_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_BETACB_CTXSW, attrib_cb_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_PAGEPOOL_CTXSW, pagepool_size); - - err = nvgpu_gr_ctx_alloc_ctxsw_buffers(g, gr_ctx, - g->gr.gr_ctx_desc, vm); - if (err != 0) { - nvgpu_err(g, "cannot allocate ctxsw buffers"); - goto fail; - } - - desc = &gr_ctx->preempt_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; - - desc = &gr_ctx->spill_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; - - desc = &gr_ctx->pagepool_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = - desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; - - desc = &gr_ctx->betacb_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = - desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; - - gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; - break; - } - case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; - break; - - default: - break; - } - - if (g->ops.gr.is_valid_compute_class(g, class)) { - switch (compute_preempt_mode) { - case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_WFI; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; - break; - case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_CTA; - p->mode = - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; - break; - case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_CILP; - p->mode = - TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; - break; - default: - break; - } - } - - if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { - msg.cmd = TEGRA_VGPU_CMD_BIND_GR_CTXSW_BUFFERS; - msg.handle = vgpu_get_handle(g); - p->tsg_id = gr_ctx->tsgid; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - if (err || msg.ret) { - err = -ENOMEM; - goto fail; - } - } - - return err; - -fail: - nvgpu_err(g, "%s failed %d", __func__, err); - return err; -} - -int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode) -{ - struct nvgpu_gr_ctx *gr_ctx; - struct gk20a *g = ch->g; - struct tsg_gk20a *tsg; - struct vm_gk20a *vm; - u32 class; - int err; - - class = ch->obj_class; - if (!class) { - return -EINVAL; - } - - tsg = tsg_gk20a_from_ch(ch); - if (!tsg) { - return -EINVAL; - } - - vm = tsg->vm; - gr_ctx = tsg->gr_ctx; - - /* skip setting anything if both modes are already set */ - if (graphics_preempt_mode && - (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { - graphics_preempt_mode = 0; - } - - if (compute_preempt_mode && - (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { - compute_preempt_mode = 0; - } - - if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) { - return 0; - } - - if (g->ops.gr.set_ctxsw_preemption_mode) { - err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class, - graphics_preempt_mode, - compute_preempt_mode); - if (err) { - nvgpu_err(g, "set_ctxsw_preemption_mode failed"); - return err; - } - } else { - err = -ENOSYS; - } - - return err; -} - -int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) -{ - struct vgpu_priv_data *priv = vgpu_get_priv_data(g); - int err; - - nvgpu_log_fn(g, " "); - - err = vgpu_gr_init_ctx_state(g); - if (err) { - return err; - } - - g->gr.ctx_vars.preempt_image_size = - priv->constants.preempt_ctx_size; - if (!g->gr.ctx_vars.preempt_image_size) { - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.h deleted file mode 100644 index 0c15a9d53..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gp10b.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VGPU_GR_GP10B_H -#define NVGPU_VGPU_GR_GP10B_H - -#include - -struct gk20a; -struct nvgpu_gr_ctx; -struct vm_gk20a; -struct channel_gk20a; - -int vgpu_gr_gp10b_init_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, - u32 class, - u32 flags); -int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, u32 class, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); -int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); -int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g); - -#endif /* NVGPU_VGPU_GR_GP10B_H */ diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.c deleted file mode 100644 index 60a6df7ce..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "gr_vgpu.h" -#include "ctx_vgpu.h" -#include "vgpu_gr_gv11b.h" - -#include "common/vgpu/gv11b/vgpu_subctx_gv11b.h" - -int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) -{ - int err; - - err = vgpu_gv11b_alloc_subctx_header(c); - if (err) { - return err; - } - - err = vgpu_gr_commit_inst(c, gpu_va); - if (err) { - vgpu_gv11b_free_subctx_header(c); - } - - return err; -} diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.h deleted file mode 100644 index 84d0c9542..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/gr/vgpu_gr_gv11b.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VGPU_GR_GV11B_H -#define NVGPU_VGPU_GR_GV11B_H - -struct channel_gk20a; - -int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); - -#endif /* NVGPU_VGPU_GR_GV11B_H */ diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 1da6feff4..f0fb1d7f9 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -64,10 +64,7 @@ #include "common/vgpu/fecs_trace_vgpu.h" #include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" #include "common/vgpu/fifo/vgpu_fifo_gv11b.h" -#include "common/vgpu/gr/vgpu_gr_gm20b.h" #include "common/vgpu/gp10b/vgpu_mm_gp10b.h" -#include "common/vgpu/gr/vgpu_gr_gp10b.h" -#include "common/vgpu/gr/vgpu_gr_gv11b.h" #include "common/falcon/falcon_gk20a.h" @@ -159,11 +156,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_tpc_num = gr_gm20b_get_tpc_num, .detect_sm_arch = vgpu_gr_detect_sm_arch, .pagepool_default_size = gr_gv11b_pagepool_default_size, - .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, + .init_ctx_state = vgpu_gr_init_ctx_state, .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx, .free_gr_ctx = vgpu_gr_free_gr_ctx, .init_ctxsw_preemption_mode = - vgpu_gr_gp10b_init_ctxsw_preemption_mode, + vgpu_gr_init_ctxsw_preemption_mode, .update_ctxsw_preemption_mode = gr_gv11b_update_ctxsw_preemption_mode, .dump_gr_regs = NULL, @@ -175,7 +172,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_max_fbps_count = vgpu_gr_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = NULL, - .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, + .init_cyclestats = vgpu_gr_init_cyclestats, .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, .bpt_reg_info = NULL, .get_access_map = gr_gv11b_get_access_map, @@ -198,7 +195,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .setup_rop_mapping = NULL, .program_zcull_mapping = NULL, .commit_global_timeslice = NULL, - .commit_inst = vgpu_gr_gv11b_commit_inst, + .commit_inst = vgpu_gr_commit_inst, .load_tpc_mask = NULL, .trigger_suspend = NULL, .wait_for_pause = gr_gk20a_wait_for_pause, @@ -222,14 +219,14 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, .disable_rd_coalesce = NULL, .set_boosted_ctx = NULL, - .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, + .set_preemption_mode = vgpu_gr_set_preemption_mode, .set_czf_bypass = NULL, .pre_process_sm_exception = NULL, .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, .init_preemption_state = NULL, .set_bes_crop_debug3 = NULL, .set_bes_crop_debug4 = NULL, - .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, + .set_ctxsw_preemption_mode = vgpu_gr_set_ctxsw_preemption_mode, .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, @@ -263,6 +260,14 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .set_debug_mode = gm20b_gr_set_debug_mode, + .get_ctx_spill_size = gv11b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gv11b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gv11b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gv11b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 62d208ab5..e5a02bb9b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2047,8 +2047,7 @@ int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_log_fn(g, " "); - size = gr->bundle_cb_default_size * - gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); + size = g->ops.gr.get_global_ctx_cb_buffer_size(g); nvgpu_log_info(g, "cb_buffer_size : %d", size); nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, @@ -2056,8 +2055,7 @@ int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR, size); - size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); + size = g->ops.gr.get_global_ctx_pagepool_buffer_size(g); nvgpu_log_info(g, "pagepool_buffer_size : %d", size); nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer, @@ -7305,3 +7303,17 @@ u32 gr_gk20a_gpccs_falcon_base_addr(void) { return gr_gpcs_gpccs_irqsset_r(); } + +u32 gk20a_gr_get_global_ctx_cb_buffer_size(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + return gr->bundle_cb_default_size * + gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); +} + +u32 gk20a_gr_get_global_ctx_pagepool_buffer_size(struct gk20a *g) +{ + return g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); +} diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 6eb17b461..9482cb671 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -617,4 +617,6 @@ void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr); u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g); u32 gr_gk20a_fecs_falcon_base_addr(void); u32 gr_gk20a_gpccs_falcon_base_addr(void); +u32 gk20a_gr_get_global_ctx_cb_buffer_size(struct gk20a *g); +u32 gk20a_gr_get_global_ctx_pagepool_buffer_size(struct gk20a *g); #endif /*__GR_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 9d9d1b0c5..3a9e8da34 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -340,6 +340,10 @@ static const struct gpu_ops gm20b_ops = { .init_gfxp_rtv_cb = NULL, .commit_gfxp_rtv_cb = NULL, .log_mme_exception = NULL, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 7fd9bf118..00985a52b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -906,17 +906,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, switch (graphics_preempt_mode) { case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - nvgpu_gr_config_get_max_tpc_count(g->gr.config); + u32 spill_size = g->ops.gr.get_ctx_spill_size(g); + u32 pagepool_size = g->ops.gr.get_ctx_pagepool_size(g); + u32 betacb_size = g->ops.gr.get_ctx_betacb_size(g); + u32 attrib_cb_size = + g->ops.gr.get_ctx_attrib_cb_size(g, betacb_size); attrib_cb_size = ALIGN(attrib_cb_size, 128); nvgpu_log_info(g, "gfxp context spill_size=%d", spill_size); @@ -2223,3 +2217,25 @@ unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g) /* 100msec @ 1GHZ */ return (100UL * 1000UL * 1000UL); } + +u32 gp10b_gr_get_ctx_spill_size(struct gk20a *g) { + return gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); +} + +u32 gp10b_gr_get_ctx_pagepool_size(struct gk20a *g) { + return g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); +} + +u32 gp10b_gr_get_ctx_betacb_size(struct gk20a *g) { + return g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); +} + +u32 gp10b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size) { + return (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + nvgpu_gr_config_get_max_tpc_count(g->gr.config); +} diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 05aa5d994..a4f898c72 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -136,5 +136,8 @@ void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g); unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); bool gr_gp10b_suspend_context(struct channel_gk20a *ch, bool *cilp_preempt_pending); - +u32 gp10b_gr_get_ctx_spill_size(struct gk20a *g); +u32 gp10b_gr_get_ctx_pagepool_size(struct gk20a *g); +u32 gp10b_gr_get_ctx_betacb_size(struct gk20a *g); +u32 gp10b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size); #endif /* NVGPU_GR_GP10B_H */ diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2a15a6ea6..75f24fd0d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -376,6 +376,14 @@ static const struct gpu_ops gp10b_ops = { .init_gfxp_rtv_cb = NULL, .commit_gfxp_rtv_cb = NULL, .log_mme_exception = NULL, + .get_ctx_spill_size = gp10b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gp10b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gp10b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gp10b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 8e013fff7..89b23a776 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -493,6 +493,14 @@ static const struct gpu_ops gv100_ops = { .init_gfxp_rtv_cb = NULL, .commit_gfxp_rtv_cb = NULL, .log_mme_exception = NULL, + .get_ctx_spill_size = gp10b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gp10b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gp10b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gp10b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 72e0cebff..60ca2b360 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1522,123 +1522,6 @@ void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) } } -int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, u32 class, - u32 graphics_preempt_mode, - u32 compute_preempt_mode) -{ - int err = 0; - - if (g->ops.gr.is_valid_gfx_class(g, class) && - g->gr.ctx_vars.force_preemption_gfxp) { - graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; - } - - if (g->ops.gr.is_valid_compute_class(g, class) && - g->gr.ctx_vars.force_preemption_cilp) { - compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; - } - - /* check for invalid combinations */ - if ((graphics_preempt_mode == 0U) && (compute_preempt_mode == 0U)) { - return -EINVAL; - } - - if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && - (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) { - return -EINVAL; - } - - /* Do not allow lower preemption modes than current ones */ - if ((graphics_preempt_mode != 0U) && - (graphics_preempt_mode < gr_ctx->graphics_preempt_mode)) { - return -EINVAL; - } - - if ((compute_preempt_mode != 0U) && - (compute_preempt_mode < gr_ctx->compute_preempt_mode)) { - return -EINVAL; - } - - /* set preemption modes */ - switch (graphics_preempt_mode) { - case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: - { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - nvgpu_gr_config_get_max_tpc_count(g->gr.config); - attrib_cb_size = ALIGN(attrib_cb_size, 128); - - nvgpu_log_info(g, "gfxp context spill_size=%d", spill_size); - nvgpu_log_info(g, "gfxp context pagepool_size=%d", pagepool_size); - nvgpu_log_info(g, "gfxp context attrib_cb_size=%d", - attrib_cb_size); - - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_PREEMPT_CTXSW, - g->gr.ctx_vars.preempt_image_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_SPILL_CTXSW, spill_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_BETACB_CTXSW, attrib_cb_size); - nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, - NVGPU_GR_CTX_PAGEPOOL_CTXSW, pagepool_size); - - if (g->ops.gr.init_gfxp_rtv_cb != NULL) { - err = g->ops.gr.init_gfxp_rtv_cb(g, gr_ctx, vm); - if (err != 0) { - nvgpu_err(g, "cannot allocate gfxp rtv_cb"); - goto fail; - } - } - - err = nvgpu_gr_ctx_alloc_ctxsw_buffers(g, gr_ctx, - g->gr.gr_ctx_desc, vm); - if (err != 0) { - nvgpu_err(g, "cannot allocate ctxsw buffers"); - goto fail; - } - - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; - break; - } - - case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; - break; - - default: - break; - } - - if (g->ops.gr.is_valid_compute_class(g, class) || - g->ops.gr.is_valid_gfx_class(g, class)) { - switch (compute_preempt_mode) { - case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: - case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: - case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: - gr_ctx->compute_preempt_mode = compute_preempt_mode; - break; - default: - break; - } - } - - return 0; - -fail: - return err; -} - void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx) { @@ -5076,3 +4959,25 @@ fail: nvgpu_mutex_release(&g->dbg_sessions_lock); return err; } + +u32 gv11b_gr_get_ctx_spill_size(struct gk20a *g) { + return gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); +} + +u32 gv11b_gr_get_ctx_pagepool_size(struct gk20a *g) { + return g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); +} + +u32 gv11b_gr_get_ctx_betacb_size(struct gk20a *g) { + return g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); +} + +u32 gv11b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size) { + return (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + nvgpu_gr_config_get_max_tpc_count(g->gr.config); +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 2c64c234a..1a5415b1b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -202,12 +202,6 @@ void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g); unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g); -int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, - struct vm_gk20a *vm, u32 class, - u32 graphics_preempt_mode, - u32 compute_preempt_mode); - void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx); int gr_gv11b_handle_ssync_hww(struct gk20a *g); @@ -231,4 +225,8 @@ void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data); void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data); void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data); +u32 gv11b_gr_get_ctx_spill_size(struct gk20a *g); +u32 gv11b_gr_get_ctx_pagepool_size(struct gk20a *g); +u32 gv11b_gr_get_ctx_betacb_size(struct gk20a *g); +u32 gv11b_gr_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size); #endif /* NVGPU_GR_GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a9c0c0269..346f0f656 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -407,7 +407,7 @@ static const struct gpu_ops gv11b_ops = { .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, .init_ecc = gv11b_ecc_init, - .set_ctxsw_preemption_mode = gr_gv11b_set_ctxsw_preemption_mode, + .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, @@ -453,6 +453,14 @@ static const struct gpu_ops gv11b_ops = { .init_gfxp_rtv_cb = NULL, .commit_gfxp_rtv_cb = NULL, .log_mme_exception = NULL, + .get_ctx_spill_size = gv11b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gv11b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gv11b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gv11b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a6d07a48c..702078bee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -519,6 +519,12 @@ struct gpu_ops { void (*commit_gfxp_rtv_cb)(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool patch); void (*log_mme_exception)(struct gk20a *g); + u32 (*get_ctx_spill_size)(struct gk20a *g); + u32 (*get_ctx_pagepool_size)(struct gk20a *g); + u32 (*get_ctx_betacb_size)(struct gk20a *g); + u32 (*get_ctx_attrib_cb_size)(struct gk20a *g, u32 betacb_size); + u32 (*get_global_ctx_cb_buffer_size)(struct gk20a *g); + u32 (*get_global_ctx_pagepool_buffer_size)(struct gk20a *g); struct { u32 (*hw_get_fecs_header_size)(void); u32 (*hw_get_gpccs_header_size)(void); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 6840fd7b1..af59bc1d7 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -516,6 +516,14 @@ static const struct gpu_ops tu104_ops = { .get_fecs_ctx_state_store_major_rev_id = gk20a_gr_get_fecs_ctx_state_store_major_rev_id, .log_mme_exception = gr_tu104_log_mme_exception, + .get_ctx_spill_size = gp10b_gr_get_ctx_spill_size, + .get_ctx_pagepool_size = gp10b_gr_get_ctx_pagepool_size, + .get_ctx_betacb_size = gp10b_gr_get_ctx_betacb_size, + .get_ctx_attrib_cb_size = gp10b_gr_get_ctx_attrib_cb_size, + .get_global_ctx_cb_buffer_size = + gk20a_gr_get_global_ctx_cb_buffer_size, + .get_global_ctx_pagepool_buffer_size = + gk20a_gr_get_global_ctx_pagepool_buffer_size, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size,