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gpu: nvgpu: move fence_gk20a to common/fence
Move gk20a/fence_gk20a.c to common/fence/fence.c Renamed gk20a_fence_from_semaphore -> nvgpu_fence_from_semaphore gk20a_fence_from_syncpt -> nvgpu_fence_from_syncpt gk20a_alloc_fence_pool -> nvgpu_fence_pool_alloc gk20a_free_fence_pool -> nvgpu_fence_pool_free gk20a_alloc_fence -> nvgpu_fence_alloc gk20a_init_fence -> nvgpu_fence_init gk20a_fence_put -> nvgpu_fence_put gk20a_fence_get -> nvgpu_fence_get gk20a_fence_wait -> nvgpu_fence_wait gk20a_fence_is_expired -> nvgpu_fence_is_expired gk20a_fence_install_fd -> nvgpu_fence_install_fd gk20a_fence_ops struct -> nvgpu_fence_ops struct gk20a_fence struct -> nvgpu_fence_type struct JIRA NVGPU-1982 Change-Id: Ife77b2c3c386ff4368683c78ca02f00c99cddb4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* GK20A Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -35,9 +35,9 @@
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#include <nvgpu/channel_sync.h>
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#include <nvgpu/channel_sync_syncpt.h>
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#include <nvgpu/channel_sync_semaphore.h>
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#include <nvgpu/fence.h>
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#include "channel_sync_priv.h"
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#include "gk20a/fence_gk20a.h"
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#include "gk20a/mm_gk20a.h"
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struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c,
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@@ -72,7 +72,7 @@ int nvgpu_channel_sync_wait_fence_fd(struct nvgpu_channel_sync *s, int fd,
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}
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int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry *entry, struct gk20a_fence *fence,
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struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence,
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bool need_sync_fence, bool register_irq)
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{
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return s->incr(s, entry, fence, need_sync_fence, register_irq);
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@@ -80,7 +80,7 @@ int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
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int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
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int wait_fence_fd, struct priv_cmd_entry *entry,
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struct gk20a_fence *fence, bool wfi, bool need_sync_fence,
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struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
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bool register_irq)
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{
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return s->incr_user(s, wait_fence_fd, entry, fence, wfi,
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