diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
index d8bcf75bc..025bf6898 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
@@ -39,6 +39,8 @@
 int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 					  u32 class_num, u32 offset, u32 data)
 {
+	int ret = 0;
+
 	nvgpu_log_fn(g, " ");
 
 	if (class_num == MAXWELL_COMPUTE_B) {
@@ -50,10 +52,15 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			g->ops.gr.init.lg_coalesce(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
 
+	if (ret != 0) {
+		goto fail;
+	}
+
 	if (class_num == MAXWELL_B) {
 		switch (offset << 2) {
 		case NVB197_SET_SHADER_EXCEPTIONS:
@@ -69,13 +76,13 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			g->ops.gr.init.lg_coalesce(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
-	return 0;
 
 fail:
-	return -EINVAL;
+	return ret;
 }
 
 void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
index 2567cf017..b6f40a979 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
@@ -194,6 +194,8 @@ void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data)
 int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 				     u32 class_num, u32 offset, u32 data)
 {
+	int ret = 0;
+
 	nvgpu_log_fn(g, " ");
 
 	if (class_num == PASCAL_COMPUTE_A) {
@@ -205,10 +207,15 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			g->ops.gr.init.lg_coalesce(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
 
+	if (ret != 0) {
+		goto fail;
+	}
+
 	if (class_num == PASCAL_A) {
 		switch (offset << 2) {
 		case NVC097_SET_SHADER_EXCEPTIONS:
@@ -236,13 +243,13 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			g->ops.gr.set_bes_crop_debug4(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
-	return 0;
 
 fail:
-	return -EINVAL;
+	return ret;
 }
 
 static void gr_gp10b_sm_lrf_ecc_overcount_war(bool single_err,
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
index e04343edb..dca04c552 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
@@ -172,6 +172,8 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data)
 int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 				     u32 class_num, u32 offset, u32 data)
 {
+	int ret = 0;
+
 	nvgpu_log_fn(g, " ");
 
 	if (class_num == VOLTA_COMPUTE_A) {
@@ -186,10 +188,15 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			gv11b_gr_intr_set_shader_cut_collector(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
 
+	if (ret != 0) {
+		goto fail;
+	}
+
 	if (class_num == VOLTA_A) {
 		switch (offset << 2) {
 		case NVC397_SET_SHADER_EXCEPTIONS:
@@ -223,13 +230,13 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			gv11b_gr_intr_set_shader_cut_collector(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
-	return 0;
 
 fail:
-	return -EINVAL;
+	return ret;
 }
 
 void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
index 836fc45ed..cd10c2e8f 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
@@ -62,6 +62,8 @@ static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data)
 int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			      u32 class_num, u32 offset, u32 data)
 {
+	int ret = 0;
+
 	nvgpu_log_fn(g, " ");
 
 	if (class_num == TURING_COMPUTE_A) {
@@ -79,10 +81,15 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			gv11b_gr_intr_set_shader_cut_collector(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
 
+	if (ret != 0) {
+		goto fail;
+	}
+
 	if (class_num == TURING_A) {
 		switch (offset << 2) {
 		case NVC597_SET_SHADER_EXCEPTIONS:
@@ -119,13 +126,13 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			gv11b_gr_intr_set_shader_cut_collector(g, data);
 			break;
 		default:
-			goto fail;
+			ret = -EINVAL;
+			break;
 		}
 	}
-	return 0;
 
 fail:
-	return -EINVAL;
+	return ret;
 }
 
 void tu104_gr_intr_enable_gpc_exceptions(struct gk20a *g,