From 328fcb4c76a5d157443c94e7f5b3f41f143d741b Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 7 Nov 2018 13:04:30 -0500 Subject: [PATCH] gpu: nvgpu: add HAL for reading gcplex fuse This adds a HAL interface for reading the gcplex fuse and sets up the HAL for the appropriate devices. JIRA NVGPU-938 Change-Id: I83ed8b78b70f5b24ac3921d174c299abc91e286d Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1945141 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | 2 +- drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c | 5 +++-- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 +++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 + 7 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c index 8f18ca930..67db3598e 100644 --- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c @@ -45,7 +45,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g) return 0; } - if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config) != 0) { + if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) { nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); return -EINVAL; } diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c index 56920b843..f9c557058 100644 --- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c @@ -46,7 +46,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) return 0; } - if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config) != 0) { + if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) { nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); return -EINVAL; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c index 0cc1e56f7..9fb53286c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c @@ -267,8 +267,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g) g->ops.fuse.fuse_opt_sec_debug_en(g)); nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", g->ops.fuse.fuse_opt_priv_sec_en(g)); - nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); - nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); + if (g->ops.fuse.read_gcplex_config_fuse(g, &val) != 0) { + nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); + } } bool gm20b_pmu_is_debug_mode_en(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index b66538a40..d6d66ec6b 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "common/clock_gating/gm20b_gating_reglist.h" #include "common/bus/bus_gm20b.h" @@ -674,6 +675,8 @@ static const struct gpu_ops gm20b_ops = { .read_vin_cal_fuse_rev = NULL, .read_vin_cal_slope_intercept_fuse = NULL, .read_vin_cal_gain_offset_fuse = NULL, + .read_gcplex_config_fuse = + nvgpu_tegra_fuse_read_gcplex_config_fuse, }, .acr = { .acr_sw_init = nvgpu_gm20b_acr_sw_init, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 08077e1bd..745c3af28 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "common/bus/bus_gk20a.h" #include "common/clock_gating/gp10b_gating_reglist.h" @@ -742,6 +743,8 @@ static const struct gpu_ops gp10b_ops = { .read_vin_cal_fuse_rev = NULL, .read_vin_cal_slope_intercept_fuse = NULL, .read_vin_cal_gain_offset_fuse = NULL, + .read_gcplex_config_fuse = + nvgpu_tegra_fuse_read_gcplex_config_fuse, }, .acr = { .acr_sw_init = nvgpu_gm20b_acr_sw_init, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 918193244..ab664b7c5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -22,6 +22,7 @@ * DEALINGS IN THE SOFTWARE. */ #include +#include #include "common/bus/bus_gk20a.h" #include "common/bus/bus_gp10b.h" @@ -868,6 +869,8 @@ static const struct gpu_ops gv11b_ops = { .read_vin_cal_fuse_rev = NULL, .read_vin_cal_slope_intercept_fuse = NULL, .read_vin_cal_gain_offset_fuse = NULL, + .read_gcplex_config_fuse = + nvgpu_tegra_fuse_read_gcplex_config_fuse, }, .acr = { .acr_sw_init = nvgpu_gv11b_acr_sw_init, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 6a485fa0c..5ee05f679 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1325,6 +1325,7 @@ struct gpu_ops { int (*read_vin_cal_gain_offset_fuse)(struct gk20a *g, u32 vin_id, s8 *gain, s8 *offset); + int (*read_gcplex_config_fuse)(struct gk20a *g, u32 *val); } fuse; struct { int (*init)(struct gk20a *g);