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gpu: nvgpu: gk20a: Qualify unsigned HW constants

Browse Source 
Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.

Change-Id: I6f23cb6be4000300388bf17a04103d01571fc250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567983
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-09-25 13:24:24 -07:00
committed by mobile promotions
parent 7755605daf
commit 32ed45a463
24 changed files with 2443 additions and 2443 deletions
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56
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
View File

@@ -58,114 +58,114 @@
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700;
return 0x00001700U;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffff) << 0;
return (v & 0xffffffU) << 0U;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000;
return 0x2000000U;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000;
return 0x3000000U;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010;
return 0x00000010U;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704;
return 0x00001704U;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 bus_bar2_block_r(void)
{
return 0x00001714;
return 0x00001714U;
}
static inline u32 bus_bar2_block_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar2_block_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 bus_bar2_block_mode_virtual_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100;
return 0x00001100U;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return 0x1 << 1;
return 0x1U << 1U;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return 0x1 << 2;
return 0x1U << 2U;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return 0x1 << 3;
return 0x1U << 3U;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140;
return 0x00001140U;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return 0x1 << 1;
return 0x1U << 1U;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return 0x1 << 2;
return 0x1U << 2U;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return 0x1 << 3;
return 0x1U << 3U;
}
#endif

52
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
View File

@@ -58,106 +58,106 @@
static inline u32 ccsr_channel_inst_r(u32 i)
{
return 0x00800000 + i*8;
return 0x00800000U + i*8U;
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00000080;
return 0x00000080U;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 ccsr_channel_r(u32 i)
{
return 0x00800004 + i*8;
return 0x00800004U + i*8U;
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00000080;
return 0x00000080U;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1) << 10;
return (v & 0x1U) << 10U;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400;
return 0x400U;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800;
return 0x800U;
}
static inline u32 ccsr_channel_runlist_f(u32 v)
{
return (v & 0xf) << 16;
return (v & 0xfU) << 16U;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24) & 0xf;
return (r >> 24U) & 0xfU;
}
static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
{
return 0x0000000a;
return 0x0000000aU;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
{
return 0x0000000b;
return 0x0000000bU;
}
static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
{
return 0x0000000d;
return 0x0000000dU;
}
static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
{
return 0x0000000e;
return 0x0000000eU;
}
static inline u32 ccsr_channel_next_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28) & 0x1;
return (r >> 28U) & 0x1U;
}
#endif

14
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h
View File

@@ -58,30 +58,30 @@
static inline u32 ce2_intr_status_r(void)
{
return 0x00106908;
return 0x00106908U;
}
static inline u32 ce2_intr_status_blockpipe_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ce2_intr_status_blockpipe_reset_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 ce2_intr_status_launcherr_pending_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 ce2_intr_status_launcherr_reset_f(void)
{
return 0x4;
return 0x4U;
}
#endif

194
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h
View File

@@ -58,390 +58,390 @@
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100;
return 0x00000100U;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008;
return 0x00000008U;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010;
return 0x00000010U;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0;
return 0x000000f0U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014;
return 0x00000014U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018;
return 0x00000018U;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001c;
return 0x0000001cU;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020;
return 0x00000020U;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028;
return 0x00000028U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{
return 0x7 << 0;
return 0x7U << 0U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
{
return 0x7 << 3;
return 0x7U << 3U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002c;
return 0x0000002cU;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4;
return 0x000000f4U;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8;
return 0x000000f8U;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fc;
return 0x000000fcU;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0de;
return 0x600dc0deU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4;
return 0x000000f4U;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16) & 0xffff;
return (r >> 16U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8;
return 0x000000f8U;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fc;
return 0x000000fcU;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becab;
return 0xad0becabU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ec;
return 0x000000ecU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16) & 0xff;
return (r >> 16U) & 0xffU;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100;
return 0x00000100U;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000005;
return 0x00000005U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
{
return 0x000000a0;
return 0x000000a0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
{
return 2;
return 2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
{
return (v & 0x3) << 0;
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
{
return 0x3 << 0;
return 0x3U << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
{
return (r >> 0) & 0x3;
return (r >> 0U) & 0x3U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
{
return 0x000000a4;
return 0x000000a4U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
{
return 0x000000a8;
return 0x000000a8U;
}
static inline u32 ctxsw_prog_main_image_misc_options_o(void)
{
return 0x0000003c;
return 0x0000003cU;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
{
return 0x1 << 3;
return 0x1U << 3U;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000ac;
return 0x000000acU;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
{
return (v & 0xffff) << 0;
return (v & 0xffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
{
return 0x000000b0;
return 0x000000b0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
{
return 0xfffffff << 0;
return 0xfffffffU << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
{
return 0x3 << 28;
return 0x3U << 28U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
{
return 0x000000b4;
return 0x000000b4U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
{
return 0x00000080;
return 0x00000080U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
{
return 0x00000020;
return 0x00000020U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
{
return 0x600dbeef;
return 0x600dbeefU;
}
static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
{
return 0x00000008;
return 0x00000008U;
}
static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
{
return 0x00000010;
return 0x00000010U;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
{
return 0x00000014;
return 0x00000014U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
{
return 0x00000018;
return 0x00000018U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
{
return 0x0000001c;
return 0x0000001cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
{
return (v & 0xffffff) << 0;
return (v & 0xffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
{
return (r >> 0) & 0xffffff;
return (r >> 0U) & 0xffffffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
{
return (v & 0xff) << 24;
return (v & 0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
{
return 0xff << 24;
return 0xffU << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
{
return (r >> 24) & 0xff;
return (r >> 24U) & 0xffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
{
return 0x2000000;
return 0x2000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
{
return 0x0000000a;
return 0x0000000aU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
{
return 0xa000000;
return 0xa000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
{
return 0x0000000b;
return 0x0000000bU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
{
return 0xb000000;
return 0xb000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
{
return 0xc000000;
return 0xc000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
{
return 0x0000000d;
return 0x0000000dU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
{
return 0xd000000;
return 0xd000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
{
return 0x3000000;
return 0x3000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
{
return 0x4000000;
return 0x4000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
{
return 0x00000005;
return 0x00000005U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
{
return 0x5000000;
return 0x5000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
{
return 0x000000ff;
return 0x000000ffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
{
return 0xff000000;
return 0xff000000U;
}
#endif

102
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h
View File

@@ -58,206 +58,206 @@
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80;
return 0x00100c80U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15) & 0x1;
return (r >> 15U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16) & 0xff;
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8;
return 0x00100cb8U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffff) << 4;
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbc;
return 0x00100cbcU;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1;
return 1U;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1) << 31;
return (v & 0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return 0x1 << 31;
return 0x1U << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8;
return 0x00100cc8U;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2;
return 2U;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3) << 0;
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return 0x3 << 0;
return 0x3U << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0) & 0x3;
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
{
return (v & 0xfffffff) << 4;
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100ccc;
return 0x00100cccU;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
{
return (v & 0xfffffff) << 4;
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4;
return 0x00100cc4U;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16) & 0x1;
return (r >> 16U) & 0x1U;
}
static inline u32 fb_mmu_debug_ctrl_debug_m(void)
{
return 0x1 << 16;
return 0x1U << 16U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0;
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2) & 0x1;
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10;
return 0x00100c10U;
}
#endif

280
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
View File

@@ -58,562 +58,562 @@
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254;
return 0x00002254U;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270;
return 0x00002270U;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274;
return 0x00002274U;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xf) << 20;
return (v & 0xfU) << 20U;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return 0x00002280 + i*8;
return 0x00002280U + i*8U;
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return 0x00002284 + i*8;
return 0x00002284U + i*8U;
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffff) << 0;
return (v & 0xffffU) << 0U;
}
static inline u32 fifo_eng_runlist_length_max_v(void)
{
return 0x0000ffff;
return 0x0000ffffU;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 fifo_runlist_timeslice_r(u32 i)
{
return 0x00002310 + i*4;
return 0x00002310U + i*4U;
}
static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
{
return 0x80;
return 0x80U;
}
static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
{
return 0x3000;
return 0x3000U;
}
static inline u32 fifo_runlist_timeslice_enable_true_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 fifo_eng_timeout_r(void)
{
return 0x00002a0c;
return 0x00002a0cU;
}
static inline u32 fifo_eng_timeout_period_max_f(void)
{
return 0x7fffffff;
return 0x7fffffffU;
}
static inline u32 fifo_eng_timeout_detection_enabled_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 fifo_eng_timeout_detection_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return 0x00002350 + i*4;
return 0x00002350U + i*4U;
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return 0x00002390 + i*4;
return 0x00002390U + i*4U;
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100;
return 0x00002100U;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 fifo_intr_0_pio_error_pending_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 fifo_intr_0_pio_error_reset_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000;
return 0x800000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000;
return 0x800000U;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000;
return 0x8000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000;
return 0x8000000U;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000;
return 0x40000000U;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140;
return 0x00002140U;
}
static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
{
return (v & 0x1) << 8;
return (v & 0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return 0x1 << 8;
return 0x1U << 8U;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1) << 28;
return (v & 0x1U) << 28U;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return 0x1 << 28;
return 0x1U << 28U;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528;
return 0x00002528U;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252c;
return 0x0000252cU;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254c;
return 0x0000254cU;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000a;
return 0x0000000aU;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256c;
return 0x0000256cU;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259c;
return 0x0000259cU;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return 0x00002800 + i*16;
return 0x00002800U + i*16U;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0) & 0xfffffff;
return (r >> 0U) & 0xfffffffU;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return 0x00002804 + i*16;
return 0x00002804U + i*16U;
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return 0x00002808 + i*16;
return 0x00002808U + i*16U;
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return 0x0000280c + i*16;
return 0x0000280cU + i*16U;
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0) & 0xf;
return (r >> 0U) & 0xfU;
}
static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
{
return (r >> 7) & 0x1;
return (r >> 7U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
{
return (r >> 6) & 0x1;
return (r >> 6U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8) & 0x1f;
return (r >> 8U) & 0x1fU;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0;
return 0x000025a0U;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
{
return (r >> (0 + i*1)) & 0x1;
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00;
return 0x00002a00U;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04;
return 0x00002a04U;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return 0x3fffffff << 0;
return 0x3fffffffU << 0U;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffff;
return 0x3fffffffU;
}
static inline u32 fifo_pb_timeout_r(void)
{
return 0x00002a08;
return 0x00002a08U;
}
static inline u32 fifo_pb_timeout_detection_enabled_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262c;
return 0x0000262cU;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630;
return 0x00002630U;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return 0x1 << (0 + i*1);
return 0x1U << (0U + i*1U);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634;
return 0x00002634U;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 fifo_preempt_type_tsg_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return 0x00002a30 + i*4;
return 0x00002a30U + i*4U;
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1f) << 0;
return (v & 0x1fU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1) << 8;
return (v & 0x1U) << 8U;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return 0x00002640 + i*8;
return 0x00002640U + i*8U;
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0) & 0xfff;
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12) & 0x1;
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_engine_status_id_type_tsgid_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13) & 0x7;
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005;
return 0x00000005U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006;
return 0x00000006U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007;
return 0x00000007U;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16) & 0xfff;
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28) & 0x1;
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30) & 0x1;
return (r >> 30U) & 0x1U;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15) & 0x1;
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000;
return 0x8000U;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return 0x00003080 + i*4;
return 0x00003080U + i*4U;
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0) & 0xfff;
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12) & 0x1;
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13) & 0x7;
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005;
return 0x00000005U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006;
return 0x00000006U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007;
return 0x00000007U;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16) & 0xfff;
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28) & 0x1;
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15) & 0x1;
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001;
return 0x00000001U;
}
#endif

64
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h
View File

@@ -58,130 +58,130 @@
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004;
return 0x00070004U;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010;
return 0x00070010U;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_r(void)
{
return 0x0007000c;
return 0x0007000cU;
}
static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000;
return 0x00070000U;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
#endif

570
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h
View File

File diff suppressed because it is too large Load Diff

1844
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
View File

File diff suppressed because it is too large Load Diff

198
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h
View File

@@ -58,398 +58,398 @@
static inline u32 ltc_pltcg_base_v(void)
{
return 0x00140000;
return 0x00140000U;
}
static inline u32 ltc_pltcg_extent_v(void)
{
return 0x0017ffff;
return 0x0017ffffU;
}
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x001410c8;
return 0x001410c8U;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00141200;
return 0x00141200U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017ea00;
return 0x0017ea00U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00141104;
return 0x00141104U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16) & 0x3;
return (r >> 16U) & 0x3U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e8c8;
return 0x0017e8c8U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2) & 0x1;
return (r >> 2U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x001410c8;
return 0x001410c8U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e8cc;
return 0x0017e8ccU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e8d0;
return 0x0017e8d0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0001ffff;
return 0x0001ffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e8d4;
return 0x0017e8d4U;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000b;
return 0x0000000bU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0) & 0x3ffffff;
return (r >> 0U) & 0x3ffffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e8dc;
return 0x0017e8dcU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24) & 0xf;
return (r >> 24U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r)
{
return (r >> 28) & 0xf;
return (r >> 28U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e91c;
return 0x0017e91cU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1f) << 16;
return (v & 0x1fU) << 16U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017ea44;
return 0x0017ea44U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xf) << 0;
return (v & 0xfU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return 0x0017ea48 + i*4;
return 0x0017ea48U + i*4U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017ea58;
return 0x0017ea58U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32;
return 32U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return 0xffffffff << 0;
return 0xffffffffU << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e924;
return 0x0017e924U;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e828;
return 0x0017e828U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140828;
return 0x00140828U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_intr_r(void)
{
return 0x00140820;
return 0x00140820U;
}
static inline u32 ltc_ltcs_ltss_intr_r(void)
{
return 0x0017e820;
return 0x0017e820U;
}
static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
{
return 0x1 << 20;
return 0x1U << 20U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
{
return 0x1 << 21;
return 0x1U << 21U;
}
static inline u32 ltc_ltc0_lts0_intr_r(void)
{
return 0x00141020;
return 0x00141020U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
{
return 0x0017e910;
return 0x0017e910U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
{
return (r >> 8) & 0xf;
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
{
return 0x300;
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
{
return (r >> 28) & 0x1;
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
{
return (r >> 29) & 0x1;
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
{
return (r >> 30) & 0x1;
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
{
return 0x40000000;
return 0x40000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
{
return 0x0017e914;
return 0x0017e914U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
{
return (r >> 8) & 0xf;
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
{
return 0x300;
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
{
return (r >> 16) & 0x1;
return (r >> 16U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
{
return (r >> 28) & 0x1;
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
{
return (r >> 29) & 0x1;
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
{
return (r >> 30) & 0x1;
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
{
return 0x40000000;
return 0x40000000U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
{
return 0x00140910;
return 0x00140910U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
{
return 0x00140914;
return 0x00140914U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1;
return 0x1U;
}
#endif

116
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h
View File

@@ -58,234 +58,234 @@
static inline u32 mc_boot_0_r(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 mc_boot_0_architecture_v(u32 r)
{
return (r >> 24) & 0x1f;
return (r >> 24U) & 0x1fU;
}
static inline u32 mc_boot_0_implementation_v(u32 r)
{
return (r >> 20) & 0xf;
return (r >> 20U) & 0xfU;
}
static inline u32 mc_boot_0_major_revision_v(u32 r)
{
return (r >> 4) & 0xf;
return (r >> 4U) & 0xfU;
}
static inline u32 mc_boot_0_minor_revision_v(u32 r)
{
return (r >> 0) & 0xf;
return (r >> 0U) & 0xfU;
}
static inline u32 mc_intr_0_r(void)
{
return 0x00000100;
return 0x00000100U;
}
static inline u32 mc_intr_0_pfifo_pending_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 mc_intr_0_pgraph_pending_f(void)
{
return 0x1000;
return 0x1000U;
}
static inline u32 mc_intr_0_pmu_pending_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 mc_intr_0_ltc_pending_f(void)
{
return 0x2000000;
return 0x2000000U;
}
static inline u32 mc_intr_0_priv_ring_pending_f(void)
{
return 0x40000000;
return 0x40000000U;
}
static inline u32 mc_intr_0_pbus_pending_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 mc_intr_1_r(void)
{
return 0x00000104;
return 0x00000104U;
}
static inline u32 mc_intr_mask_0_r(void)
{
return 0x00000640;
return 0x00000640U;
}
static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 mc_intr_en_0_r(void)
{
return 0x00000140;
return 0x00000140U;
}
static inline u32 mc_intr_en_0_inta_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 mc_intr_en_0_inta_hardware_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 mc_intr_mask_1_r(void)
{
return 0x00000644;
return 0x00000644U;
}
static inline u32 mc_intr_mask_1_pmu_s(void)
{
return 1;
return 1U;
}
static inline u32 mc_intr_mask_1_pmu_f(u32 v)
{
return (v & 0x1) << 24;
return (v & 0x1U) << 24U;
}
static inline u32 mc_intr_mask_1_pmu_m(void)
{
return 0x1 << 24;
return 0x1U << 24U;
}
static inline u32 mc_intr_mask_1_pmu_v(u32 r)
{
return (r >> 24) & 0x1;
return (r >> 24U) & 0x1U;
}
static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 mc_intr_en_1_r(void)
{
return 0x00000144;
return 0x00000144U;
}
static inline u32 mc_intr_en_1_inta_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 mc_intr_en_1_inta_hardware_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 mc_enable_r(void)
{
return 0x00000200;
return 0x00000200U;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1;
return 1U;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_m(void)
{
return 0x1 << 4;
return 0x1U << 4U;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4) & 0x1;
return (r >> 4U) & 0x1U;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 mc_enable_ce0_m(void)
{
return 0x1 << 6;
return 0x1U << 6U;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000;
return 0x1000U;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13) & 0x1;
return (r >> 13U) & 0x1U;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000;
return 0x2000U;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 mc_enable_ce2_m(void)
{
return 0x1 << 21;
return 0x1U << 21U;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000;
return 0x200000U;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000;
return 0x8000000U;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204;
return 0x00000204U;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1;
return 1U;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_m(void)
{
return 0x1 << 0;
return 0x1U << 0U;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1) << (0 + i*1);
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 mc_elpg_enable_r(void)
{
return 0x0000020c;
return 0x0000020cU;
}
static inline u32 mc_elpg_enable_xbar_enabled_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 mc_elpg_enable_pfb_enabled_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 mc_elpg_enable_hub_enabled_f(void)
{
return 0x20000000;
return 0x20000000U;
}
#endif

250
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
View File

@@ -58,502 +58,502 @@
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004;
return 0x10000004U;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0) & 0xff;
return (r >> 0U) & 0xffU;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffff) << 10;
return (v & 0x1fffffU) << 10U;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10) & 0x1fffff;
return (r >> 10U) & 0x1fffffU;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return 0x00040048 + i*8192;
return 0x00040048U + i*8192U;
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffff) << 3;
return (v & 0x1fffffffU) << 3U;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3;
return 3U;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return 0x0004004c + i*8192;
return 0x0004004cU + i*8192U;
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1f) << 16;
return (v & 0x1fU) << 16U;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return 0x00040050 + i*8192;
return 0x00040050U + i*8192U;
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return 0x00040014 + i*8192;
return 0x00040014U + i*8192U;
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return 0x00040000 + i*8192;
return 0x00040000U + i*8192U;
}
static inline u32 pbdma_timeout_r(u32 i)
{
return 0x0004012c + i*8192;
return 0x0004012cU + i*8192U;
}
static inline u32 pbdma_timeout__size_1_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 pbdma_timeout_period_m(void)
{
return 0xffffffff << 0;
return 0xffffffffU << 0U;
}
static inline u32 pbdma_timeout_period_max_f(void)
{
return 0xffffffff;
return 0xffffffffU;
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return 0x00040054 + i*8192;
return 0x00040054U + i*8192U;
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return 0x00040058 + i*8192;
return 0x00040058U + i*8192U;
}
static inline u32 pbdma_get_r(u32 i)
{
return 0x00040018 + i*8192;
return 0x00040018U + i*8192U;
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return 0x0004001c + i*8192;
return 0x0004001cU + i*8192U;
}
static inline u32 pbdma_put_r(u32 i)
{
return 0x0004005c + i*8192;
return 0x0004005cU + i*8192U;
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return 0x00040060 + i*8192;
return 0x00040060U + i*8192U;
}
static inline u32 pbdma_formats_r(u32 i)
{
return 0x0004009c + i*8192;
return 0x0004009cU + i*8192U;
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return 0x00040084 + i*8192;
return 0x00040084U + i*8192U;
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000;
return 0x400000U;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 pbdma_pb_header_type_non_inc_f(void)
{
return 0x60000000;
return 0x60000000U;
}
static inline u32 pbdma_hdr_shadow_r(u32 i)
{
return 0x00040118 + i*8192;
return 0x00040118U + i*8192U;
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return 0x00040094 + i*8192;
return 0x00040094U + i*8192U;
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000;
return 0x10000000U;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 pbdma_method0_r(u32 i)
{
return 0x000400c0 + i*8192;
return 0x000400c0U + i*8192U;
}
static inline u32 pbdma_method0_addr_f(u32 v)
{
return (v & 0xfff) << 2;
return (v & 0xfffU) << 2U;
}
static inline u32 pbdma_method0_addr_v(u32 r)
{
return (r >> 2) & 0xfff;
return (r >> 2U) & 0xfffU;
}
static inline u32 pbdma_method0_subch_v(u32 r)
{
return (r >> 16) & 0x7;
return (r >> 16U) & 0x7U;
}
static inline u32 pbdma_method0_first_true_f(void)
{
return 0x400000;
return 0x400000U;
}
static inline u32 pbdma_method0_valid_true_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 pbdma_method1_r(u32 i)
{
return 0x000400c8 + i*8192;
return 0x000400c8U + i*8192U;
}
static inline u32 pbdma_method2_r(u32 i)
{
return 0x000400d0 + i*8192;
return 0x000400d0U + i*8192U;
}
static inline u32 pbdma_method3_r(u32 i)
{
return 0x000400d8 + i*8192;
return 0x000400d8U + i*8192U;
}
static inline u32 pbdma_data0_r(u32 i)
{
return 0x000400c4 + i*8192;
return 0x000400c4U + i*8192U;
}
static inline u32 pbdma_target_r(u32 i)
{
return 0x000400ac + i*8192;
return 0x000400acU + i*8192U;
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1f;
return 0x1fU;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return 0x00040030 + i*8192;
return 0x00040030U + i*8192U;
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
{
return (v & 0xf) << 11;
return (v & 0xfU) << 11U;
}
static inline u32 pbdma_acquire_timeout_exp_max_v(void)
{
return 0x0000000f;
return 0x0000000fU;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800;
return 0x7800U;
}
static inline u32 pbdma_acquire_timeout_man_f(u32 v)
{
return (v & 0xffff) << 15;
return (v & 0xffffU) << 15U;
}
static inline u32 pbdma_acquire_timeout_man_max_v(void)
{
return 0x0000ffff;
return 0x0000ffffU;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000;
return 0x7fff8000U;
}
static inline u32 pbdma_acquire_timeout_en_enable_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_status_r(u32 i)
{
return 0x00040100 + i*8192;
return 0x00040100U + i*8192U;
}
static inline u32 pbdma_channel_r(u32 i)
{
return 0x00040120 + i*8192;
return 0x00040120U + i*8192U;
}
static inline u32 pbdma_signature_r(u32 i)
{
return 0x00040010 + i*8192;
return 0x00040010U + i*8192U;
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xface;
return 0xfaceU;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_userd_r(u32 i)
{
return 0x00040008 + i*8192;
return 0x00040008U + i*8192U;
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffff) << 9;
return (v & 0x7fffffU) << 9U;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return 0x0004000c + i*8192;
return 0x0004000cU + i*8192U;
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return 0x000400e4 + i*8192;
return 0x000400e4U + i*8192U;
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return 0x00040108 + i*8192;
return 0x00040108U + i*8192U;
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40;
return 0x40U;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80;
return 0x80U;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200;
return 0x200U;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400;
return 0x400U;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800;
return 0x800U;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000;
return 0x1000U;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000;
return 0x2000U;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000;
return 0x4000U;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000;
return 0x8000U;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000;
return 0x20000U;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000;
return 0x40000U;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000;
return 0x80000U;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000;
return 0x200000U;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000;
return 0x400000U;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000;
return 0x800000U;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000;
return 0x2000000U;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000;
return 0x4000000U;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000;
return 0x8000000U;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000;
return 0x40000000U;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return 0x00040148 + i*8192;
return 0x00040148U + i*8192U;
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return 0x0004010c + i*8192;
return 0x0004010cU + i*8192U;
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return 0x0004014c + i*8192;
return 0x0004014cU + i*8192U;
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return 0x0004013c + i*8192;
return 0x0004013cU + i*8192U;
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100;
return 0x100U;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008;
return 0x00000008U;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return 0x000400a4 + i*8192;
return 0x000400a4U + i*8192U;
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return 0x000400a8 + i*8192;
return 0x000400a8U + i*8192U;
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0) & 0x3;
return (r >> 0U) & 0x3U;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4) & 0x1;
return (r >> 4U) & 0x1U;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8) & 0xff;
return (r >> 8U) & 0xffU;
}
#endif

76
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h
View File

@@ -58,154 +58,154 @@
static inline u32 perf_pmasys_control_r(void)
{
return 0x001b4000;
return 0x001b4000U;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
return (r >> 4) & 0x1;
return (r >> 4U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
{
return (v & 0x1) << 5;
return (v & 0x1U) << 5U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
{
return (r >> 5) & 0x1;
return (r >> 5U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x001b4070;
return 0x001b4070U;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 perf_pmasys_mem_block_target_f(u32 v)
{
return (v & 0x3) << 28;
return (v & 0x3U) << 28U;
}
static inline u32 perf_pmasys_mem_block_target_v(u32 r)
{
return (r >> 28) & 0x3;
return (r >> 28U) & 0x3U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
{
return (v & 0x1) << 31;
return (v & 0x1U) << 31U;
}
static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 perf_pmasys_mem_block_valid_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 perf_pmasys_mem_block_valid_true_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x001b4074;
return 0x001b4074U;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
return (v & 0x7ffffff) << 5;
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x001b4078;
return 0x001b4078U;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x001b407c;
return 0x001b407cU;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
return (v & 0x7ffffff) << 5;
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x001b4084;
return 0x001b4084U;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
return (v & 0xfffffff) << 4;
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x001b4088;
return 0x001b4088U;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
return (v & 0xfffffff) << 4;
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x001b40a4;
return 0x001b40a4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
{
return 0x10;
return 0x10U;
}
#endif

2
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h
View File

@@ -58,6 +58,6 @@
static inline u32 pram_data032_r(u32 i)
{
return 0x00700000 + i*4;
return 0x00700000U + i*4U;
}
#endif

50
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
View File

@@ -58,102 +58,102 @@
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004c;
return 0x0012004cU;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return 0x3f << 0;
return 0x3fU << 0U;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0) & 0x3f;
return (r >> 0U) & 0x3fU;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048;
return 0x00120048U;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050;
return 0x00120050U;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058;
return 0x00120058U;
}
static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
{
return (r >> 2) & 0x1;
return (r >> 2U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
{
return (r >> 8) & 0x1;
return (r >> 8U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005c;
return 0x0012005cU;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060;
return 0x00120060U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074;
return 0x00120074U;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0) & 0x1f;
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078;
return 0x00120078U;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0) & 0x1f;
return (r >> 0U) & 0x1fU;
}
#endif

10
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
View File

@@ -58,22 +58,22 @@
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{
return 0x00128300 + i*4;
return 0x00128300U + i*4U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
{
return 0x00128120;
return 0x00128120U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
{
return 0x00128124;
return 0x00128124U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
{
return 0x00128128;
return 0x00128128U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
{
return 0x0012812c;
return 0x0012812cU;
}
#endif

16
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
View File

@@ -58,34 +58,34 @@
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{
return 0x00122300 + i*4;
return 0x00122300U + i*4U;
}
static inline u32 pri_ringstation_sys_decode_config_r(void)
{
return 0x00122204;
return 0x00122204U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
{
return 0x7 << 0;
return 0x7U << 0U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
{
return 0x00122120;
return 0x00122120U;
}
static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
{
return 0x00122124;
return 0x00122124U;
}
static inline u32 pri_ringstation_sys_priv_error_info_r(void)
{
return 0x00122128;
return 0x00122128U;
}
static inline u32 pri_ringstation_sys_priv_error_code_r(void)
{
return 0x0012212c;
return 0x0012212cU;
}
#endif

52
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h
View File

@@ -58,106 +58,106 @@
static inline u32 proj_gpc_base_v(void)
{
return 0x00500000;
return 0x00500000U;
}
static inline u32 proj_gpc_shared_base_v(void)
{
return 0x00418000;
return 0x00418000U;
}
static inline u32 proj_gpc_stride_v(void)
{
return 0x00008000;
return 0x00008000U;
}
static inline u32 proj_ltc_stride_v(void)
{
return 0x00002000;
return 0x00002000U;
}
static inline u32 proj_lts_stride_v(void)
{
return 0x00000400;
return 0x00000400U;
}
static inline u32 proj_fbpa_stride_v(void)
{
return 0x00001000;
return 0x00001000U;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000;
return 0x00003000U;
}
static inline u32 proj_ppc_in_gpc_shared_base_v(void)
{
return 0x00003e00;
return 0x00003e00U;
}
static inline u32 proj_ppc_in_gpc_stride_v(void)
{
return 0x00000200;
return 0x00000200U;
}
static inline u32 proj_rop_base_v(void)
{
return 0x00410000;
return 0x00410000U;
}
static inline u32 proj_rop_shared_base_v(void)
{
return 0x00408800;
return 0x00408800U;
}
static inline u32 proj_rop_stride_v(void)
{
return 0x00000400;
return 0x00000400U;
}
static inline u32 proj_tpc_in_gpc_base_v(void)
{
return 0x00004000;
return 0x00004000U;
}
static inline u32 proj_tpc_in_gpc_stride_v(void)
{
return 0x00000800;
return 0x00000800U;
}
static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800;
return 0x00001800U;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 proj_scal_max_gpcs_v(void)
{
return 0x00000020;
return 0x00000020U;
}
static inline u32 proj_scal_max_tpc_per_gpc_v(void)
{
return 0x00000008;
return 0x00000008U;
}
#endif

362
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
View File

@@ -58,726 +58,726 @@
static inline u32 pwr_falcon_irqsset_r(void)
{
return 0x0010a000;
return 0x0010a000U;
}
static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
{
return 0x40;
return 0x40U;
}
static inline u32 pwr_falcon_irqsclr_r(void)
{
return 0x0010a004;
return 0x0010a004U;
}
static inline u32 pwr_falcon_irqstat_r(void)
{
return 0x0010a008;
return 0x0010a008U;
}
static inline u32 pwr_falcon_irqstat_halt_true_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
{
return 0x40;
return 0x40U;
}
static inline u32 pwr_falcon_irqmode_r(void)
{
return 0x0010a00c;
return 0x0010a00cU;
}
static inline u32 pwr_falcon_irqmset_r(void)
{
return 0x0010a010;
return 0x0010a010U;
}
static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
return (v & 0x1U) << 1U;
}
static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1) << 2;
return (v & 0x1U) << 2U;
}
static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
return (v & 0x1U) << 3U;
}
static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1) << 5;
return (v & 0x1U) << 5U;
}
static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
return (v & 0x1U) << 6U;
}
static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
return (v & 0x1U) << 7U;
}
static inline u32 pwr_falcon_irqmclr_r(void)
{
return 0x0010a014;
return 0x0010a014U;
}
static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
return (v & 0x1U) << 1U;
}
static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1) << 2;
return (v & 0x1U) << 2U;
}
static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
return (v & 0x1U) << 3U;
}
static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1) << 5;
return (v & 0x1U) << 5U;
}
static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
return (v & 0x1U) << 6U;
}
static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
return (v & 0x1U) << 7U;
}
static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xff) << 8;
return (v & 0xffU) << 8U;
}
static inline u32 pwr_falcon_irqmask_r(void)
{
return 0x0010a018;
return 0x0010a018U;
}
static inline u32 pwr_falcon_irqdest_r(void)
{
return 0x0010a01c;
return 0x0010a01cU;
}
static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1) << 1;
return (v & 0x1U) << 1U;
}
static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1) << 2;
return (v & 0x1U) << 2U;
}
static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1) << 3;
return (v & 0x1U) << 3U;
}
static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1) << 5;
return (v & 0x1U) << 5U;
}
static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1) << 6;
return (v & 0x1U) << 6U;
}
static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1) << 7;
return (v & 0x1U) << 7U;
}
static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xff) << 8;
return (v & 0xffU) << 8U;
}
static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1) << 16;
return (v & 0x1U) << 16U;
}
static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1) << 17;
return (v & 0x1U) << 17U;
}
static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1) << 18;
return (v & 0x1U) << 18U;
}
static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1) << 19;
return (v & 0x1U) << 19U;
}
static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1) << 20;
return (v & 0x1U) << 20U;
}
static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1) << 21;
return (v & 0x1U) << 21U;
}
static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1) << 22;
return (v & 0x1U) << 22U;
}
static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1) << 23;
return (v & 0x1U) << 23U;
}
static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xff) << 24;
return (v & 0xffU) << 24U;
}
static inline u32 pwr_falcon_curctx_r(void)
{
return 0x0010a050;
return 0x0010a050U;
}
static inline u32 pwr_falcon_nxtctx_r(void)
{
return 0x0010a054;
return 0x0010a054U;
}
static inline u32 pwr_falcon_mailbox0_r(void)
{
return 0x0010a040;
return 0x0010a040U;
}
static inline u32 pwr_falcon_mailbox1_r(void)
{
return 0x0010a044;
return 0x0010a044U;
}
static inline u32 pwr_falcon_itfen_r(void)
{
return 0x0010a048;
return 0x0010a048U;
}
static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pwr_falcon_idlestate_r(void)
{
return 0x0010a04c;
return 0x0010a04cU;
}
static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1) & 0x7fff;
return (r >> 1U) & 0x7fffU;
}
static inline u32 pwr_falcon_os_r(void)
{
return 0x0010a080;
return 0x0010a080U;
}
static inline u32 pwr_falcon_engctl_r(void)
{
return 0x0010a0a4;
return 0x0010a0a4U;
}
static inline u32 pwr_falcon_cpuctl_r(void)
{
return 0x0010a100;
return 0x0010a100U;
}
static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1) << 1;
return (v & 0x1U) << 1U;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
{
return 0x1 << 4;
return 0x1U << 4U;
}
static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4) & 0x1;
return (r >> 4U) & 0x1U;
}
static inline u32 pwr_falcon_imemc_r(u32 i)
{
return 0x0010a180 + i*16;
return 0x0010a180U + i*16U;
}
static inline u32 pwr_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3f) << 2;
return (v & 0x3fU) << 2U;
}
static inline u32 pwr_falcon_imemc_blk_f(u32 v)
{
return (v & 0xff) << 8;
return (v & 0xffU) << 8U;
}
static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1) << 24;
return (v & 0x1U) << 24U;
}
static inline u32 pwr_falcon_imemd_r(u32 i)
{
return 0x0010a184 + i*16;
return 0x0010a184U + i*16U;
}
static inline u32 pwr_falcon_imemt_r(u32 i)
{
return 0x0010a188 + i*16;
return 0x0010a188U + i*16U;
}
static inline u32 pwr_falcon_bootvec_r(void)
{
return 0x0010a104;
return 0x0010a104U;
}
static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 pwr_falcon_dmactl_r(void)
{
return 0x0010a10c;
return 0x0010a10cU;
}
static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
{
return 0x1 << 1;
return 0x1U << 1U;
}
static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
{
return 0x1 << 2;
return 0x1U << 2U;
}
static inline u32 pwr_falcon_hwcfg_r(void)
{
return 0x0010a108;
return 0x0010a108U;
}
static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0) & 0x1ff;
return (r >> 0U) & 0x1ffU;
}
static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9) & 0x1ff;
return (r >> 9U) & 0x1ffU;
}
static inline u32 pwr_falcon_dmatrfbase_r(void)
{
return 0x0010a110;
return 0x0010a110U;
}
static inline u32 pwr_falcon_dmatrfmoffs_r(void)
{
return 0x0010a114;
return 0x0010a114U;
}
static inline u32 pwr_falcon_dmatrfcmd_r(void)
{
return 0x0010a118;
return 0x0010a118U;
}
static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1) << 4;
return (v & 0x1U) << 4U;
}
static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1) << 5;
return (v & 0x1U) << 5U;
}
static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7) << 8;
return (v & 0x7U) << 8U;
}
static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7) << 12;
return (v & 0x7U) << 12U;
}
static inline u32 pwr_falcon_dmatrffboffs_r(void)
{
return 0x0010a11c;
return 0x0010a11cU;
}
static inline u32 pwr_falcon_exterraddr_r(void)
{
return 0x0010a168;
return 0x0010a168U;
}
static inline u32 pwr_falcon_exterrstat_r(void)
{
return 0x0010a16c;
return 0x0010a16cU;
}
static inline u32 pwr_falcon_exterrstat_valid_m(void)
{
return 0x1 << 31;
return 0x1U << 31U;
}
static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
{
return 0x0010a200;
return 0x0010a200U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
{
return 4;
return 4U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xf) << 0;
return (v & 0xfU) << 0U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
{
return 0xf << 0;
return 0xfU << 0U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0) & 0xf;
return (r >> 0U) & 0xfU;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xe;
return 0xeU;
}
static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1f) << 8;
return (v & 0x1fU) << 8U;
}
static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
{
return 0x0010a20c;
return 0x0010a20cU;
}
static inline u32 pwr_falcon_dmemc_r(u32 i)
{
return 0x0010a1c0 + i*8;
return 0x0010a1c0U + i*8U;
}
static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3f) << 2;
return (v & 0x3fU) << 2U;
}
static inline u32 pwr_falcon_dmemc_offs_m(void)
{
return 0x3f << 2;
return 0x3fU << 2U;
}
static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xff) << 8;
return (v & 0xffU) << 8U;
}
static inline u32 pwr_falcon_dmemc_blk_m(void)
{
return 0xff << 8;
return 0xffU << 8U;
}
static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1) << 24;
return (v & 0x1U) << 24U;
}
static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1) << 25;
return (v & 0x1U) << 25U;
}
static inline u32 pwr_falcon_dmemd_r(u32 i)
{
return 0x0010a1c4 + i*8;
return 0x0010a1c4U + i*8U;
}
static inline u32 pwr_pmu_new_instblk_r(void)
{
return 0x0010a480;
return 0x0010a480U;
}
static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
{
return (v & 0xfffffff) << 0;
return (v & 0xfffffffU) << 0U;
}
static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
{
return 0x20000000;
return 0x20000000U;
}
static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
{
return 0x30000000;
return 0x30000000U;
}
static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
{
return (v & 0x1) << 30;
return (v & 0x1U) << 30U;
}
static inline u32 pwr_pmu_mutex_id_r(void)
{
return 0x0010a488;
return 0x0010a488U;
}
static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
{
return (r >> 0) & 0xff;
return (r >> 0U) & 0xffU;
}
static inline u32 pwr_pmu_mutex_id_value_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
{
return 0x000000ff;
return 0x000000ffU;
}
static inline u32 pwr_pmu_mutex_id_release_r(void)
{
return 0x0010a48c;
return 0x0010a48cU;
}
static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 pwr_pmu_mutex_id_release_value_m(void)
{
return 0xff << 0;
return 0xffU << 0U;
}
static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_pmu_mutex_r(u32 i)
{
return 0x0010a580 + i*4;
return 0x0010a580U + i*4U;
}
static inline u32 pwr_pmu_mutex__size_1_v(void)
{
return 0x00000010;
return 0x00000010U;
}
static inline u32 pwr_pmu_mutex_value_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 pwr_pmu_mutex_value_v(u32 r)
{
return (r >> 0) & 0xff;
return (r >> 0U) & 0xffU;
}
static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_pmu_queue_head_r(u32 i)
{
return 0x0010a4a0 + i*4;
return 0x0010a4a0U + i*4U;
}
static inline u32 pwr_pmu_queue_head__size_1_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 pwr_pmu_queue_head_address_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 pwr_pmu_queue_head_address_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pwr_pmu_queue_tail_r(u32 i)
{
return 0x0010a4b0 + i*4;
return 0x0010a4b0U + i*4U;
}
static inline u32 pwr_pmu_queue_tail__size_1_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pwr_pmu_msgq_head_r(void)
{
return 0x0010a4c8;
return 0x0010a4c8U;
}
static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pwr_pmu_msgq_tail_r(void)
{
return 0x0010a4cc;
return 0x0010a4ccU;
}
static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xffffffffU) << 0U;
}
static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
{
return (r >> 0) & 0xffffffff;
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pwr_pmu_idle_mask_r(u32 i)
{
return 0x0010a504 + i*16;
return 0x0010a504U + i*16U;
}
static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
{
return 0x200000;
return 0x200000U;
}
static inline u32 pwr_pmu_idle_count_r(u32 i)
{
return 0x0010a508 + i*16;
return 0x0010a508U + i*16U;
}
static inline u32 pwr_pmu_idle_count_value_f(u32 v)
{
return (v & 0x7fffffff) << 0;
return (v & 0x7fffffffU) << 0U;
}
static inline u32 pwr_pmu_idle_count_value_v(u32 r)
{
return (r >> 0) & 0x7fffffff;
return (r >> 0U) & 0x7fffffffU;
}
static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
{
return (v & 0x1) << 31;
return (v & 0x1U) << 31U;
}
static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
{
return 0x0010a50c + i*16;
return 0x0010a50cU + i*16U;
}
static inline u32 pwr_pmu_idle_ctrl_value_m(void)
{
return 0x3 << 0;
return 0x3U << 0U;
}
static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
{
return 0x1 << 2;
return 0x1U << 2U;
}
static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
{
return 0x0010a9f0 + i*8;
return 0x0010a9f0U + i*8U;
}
static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
{
return 0x0010a9f4 + i*8;
return 0x0010a9f4U + i*8U;
}
static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
{
return 0x0010aa30 + i*8;
return 0x0010aa30U + i*8U;
}
static inline u32 pwr_pmu_debug_r(u32 i)
{
return 0x0010a5c0 + i*4;
return 0x0010a5c0U + i*4U;
}
static inline u32 pwr_pmu_debug__size_1_v(void)
{
return 0x00000004;
return 0x00000004U;
}
static inline u32 pwr_pmu_mailbox_r(u32 i)
{
return 0x0010a450 + i*4;
return 0x0010a450U + i*4U;
}
static inline u32 pwr_pmu_mailbox__size_1_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 pwr_pmu_bar0_addr_r(void)
{
return 0x0010a7a0;
return 0x0010a7a0U;
}
static inline u32 pwr_pmu_bar0_data_r(void)
{
return 0x0010a7a4;
return 0x0010a7a4U;
}
static inline u32 pwr_pmu_bar0_ctl_r(void)
{
return 0x0010a7ac;
return 0x0010a7acU;
}
static inline u32 pwr_pmu_bar0_timeout_r(void)
{
return 0x0010a7a8;
return 0x0010a7a8U;
}
static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988;
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0;
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0 + i*4;
return 0x0010a6c0U + i*4U;
}
static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
{
return 0x0010a6e8 + i*4;
return 0x0010a6e8U + i*4U;
}
static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
{
return 0x0010a710 + i*4;
return 0x0010a710U + i*4U;
}
static inline u32 pwr_pmu_pg_intren_r(u32 i)
{
return 0x0010a760 + i*4;
return 0x0010a760U + i*4U;
}
static inline u32 pwr_fbif_transcfg_r(u32 i)
{
return 0x0010a600 + i*4;
return 0x0010a600U + i*4U;
}
static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 pwr_fbif_transcfg_mem_type_s(void)
{
return 1;
return 1U;
}
static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
{
return (v & 0x1) << 2;
return (v & 0x1U) << 2U;
}
static inline u32 pwr_fbif_transcfg_mem_type_m(void)
{
return 0x1 << 2;
return 0x1U << 2U;
}
static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
{
return (r >> 2) & 0x1;
return (r >> 2U) & 0x1U;
}
static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
{
return 0x4;
return 0x4U;
}
#endif

192
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h
View File

@@ -58,386 +58,386 @@
static inline u32 ram_in_ramfc_s(void)
{
return 4096;
return 4096U;
}
static inline u32 ram_in_ramfc_w(void)
{
return 0;
return 0U;
}
static inline u32 ram_in_page_dir_base_target_f(u32 v)
{
return (v & 0x3) << 0;
return (v & 0x3U) << 0U;
}
static inline u32 ram_in_page_dir_base_target_w(void)
{
return 128;
return 128U;
}
static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
{
return 0x3;
return 0x3U;
}
static inline u32 ram_in_page_dir_base_vol_w(void)
{
return 128;
return 128U;
}
static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 ram_in_page_dir_base_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_page_dir_base_lo_w(void)
{
return 128;
return 128U;
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129;
return 129U;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130;
return 130U;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131;
return 131U;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132;
return 132U;
}
static inline u32 ram_in_engine_cs_wfi_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 ram_in_engine_cs_wfi_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ram_in_engine_cs_fg_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 ram_in_gr_cs_w(void)
{
return 132;
return 132U;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132;
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132;
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
{
return 132;
return 132U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
{
return 133;
return 133U;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000c;
return 0x0000000cU;
}
static inline u32 ram_in_alloc_size_v(void)
{
return 0x00001000;
return 0x00001000U;
}
static inline u32 ram_fc_size_val_v(void)
{
return 0x00000200;
return 0x00000200U;
}
static inline u32 ram_fc_gp_put_w(void)
{
return 0;
return 0U;
}
static inline u32 ram_fc_userd_w(void)
{
return 2;
return 2U;
}
static inline u32 ram_fc_userd_hi_w(void)
{
return 3;
return 3U;
}
static inline u32 ram_fc_signature_w(void)
{
return 4;
return 4U;
}
static inline u32 ram_fc_gp_get_w(void)
{
return 5;
return 5U;
}
static inline u32 ram_fc_pb_get_w(void)
{
return 6;
return 6U;
}
static inline u32 ram_fc_pb_get_hi_w(void)
{
return 7;
return 7U;
}
static inline u32 ram_fc_pb_top_level_get_w(void)
{
return 8;
return 8U;
}
static inline u32 ram_fc_pb_top_level_get_hi_w(void)
{
return 9;
return 9U;
}
static inline u32 ram_fc_acquire_w(void)
{
return 12;
return 12U;
}
static inline u32 ram_fc_semaphorea_w(void)
{
return 14;
return 14U;
}
static inline u32 ram_fc_semaphoreb_w(void)
{
return 15;
return 15U;
}
static inline u32 ram_fc_semaphorec_w(void)
{
return 16;
return 16U;
}
static inline u32 ram_fc_semaphored_w(void)
{
return 17;
return 17U;
}
static inline u32 ram_fc_gp_base_w(void)
{
return 18;
return 18U;
}
static inline u32 ram_fc_gp_base_hi_w(void)
{
return 19;
return 19U;
}
static inline u32 ram_fc_gp_fetch_w(void)
{
return 20;
return 20U;
}
static inline u32 ram_fc_pb_fetch_w(void)
{
return 21;
return 21U;
}
static inline u32 ram_fc_pb_fetch_hi_w(void)
{
return 22;
return 22U;
}
static inline u32 ram_fc_pb_put_w(void)
{
return 23;
return 23U;
}
static inline u32 ram_fc_pb_put_hi_w(void)
{
return 24;
return 24U;
}
static inline u32 ram_fc_pb_header_w(void)
{
return 33;
return 33U;
}
static inline u32 ram_fc_pb_count_w(void)
{
return 34;
return 34U;
}
static inline u32 ram_fc_subdevice_w(void)
{
return 37;
return 37U;
}
static inline u32 ram_fc_formats_w(void)
{
return 39;
return 39U;
}
static inline u32 ram_fc_syncpointa_w(void)
{
return 41;
return 41U;
}
static inline u32 ram_fc_syncpointb_w(void)
{
return 42;
return 42U;
}
static inline u32 ram_fc_target_w(void)
{
return 43;
return 43U;
}
static inline u32 ram_fc_hce_ctrl_w(void)
{
return 57;
return 57U;
}
static inline u32 ram_fc_chid_w(void)
{
return 58;
return 58U;
}
static inline u32 ram_fc_chid_id_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 ram_fc_chid_id_w(void)
{
return 0;
return 0U;
}
static inline u32 ram_fc_runlist_timeslice_w(void)
{
return 62;
return 62U;
}
static inline u32 ram_fc_pb_timeslice_w(void)
{
return 63;
return 63U;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009;
return 0x00000009U;
}
static inline u32 ram_userd_chan_size_v(void)
{
return 0x00000200;
return 0x00000200U;
}
static inline u32 ram_userd_put_w(void)
{
return 16;
return 16U;
}
static inline u32 ram_userd_get_w(void)
{
return 17;
return 17U;
}
static inline u32 ram_userd_ref_w(void)
{
return 18;
return 18U;
}
static inline u32 ram_userd_put_hi_w(void)
{
return 19;
return 19U;
}
static inline u32 ram_userd_ref_threshold_w(void)
{
return 20;
return 20U;
}
static inline u32 ram_userd_top_level_get_w(void)
{
return 22;
return 22U;
}
static inline u32 ram_userd_top_level_get_hi_w(void)
{
return 23;
return 23U;
}
static inline u32 ram_userd_get_hi_w(void)
{
return 24;
return 24U;
}
static inline u32 ram_userd_gp_get_w(void)
{
return 34;
return 34U;
}
static inline u32 ram_userd_gp_put_w(void)
{
return 35;
return 35U;
}
static inline u32 ram_userd_gp_top_level_get_w(void)
{
return 22;
return 22U;
}
static inline u32 ram_userd_gp_top_level_get_hi_w(void)
{
return 23;
return 23U;
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008;
return 0x00000008U;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
return (v & 0xfff) << 0;
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1) << 13;
return (v & 0x1U) << 13U;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x2000;
return 0x2000U;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xf) << 14;
return (v & 0xfU) << 14U;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000;
return 0xc000U;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xff) << 18;
return (v & 0xffU) << 18U;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000;
return 0x2000000U;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0x3f) << 26;
return (v & 0x3fU) << 26U;
}
#endif

154
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h
View File

@@ -58,310 +58,310 @@
static inline u32 therm_use_a_r(void)
{
return 0x00020798;
return 0x00020798U;
}
static inline u32 therm_use_a_ext_therm_0_enable_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 therm_use_a_ext_therm_1_enable_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 therm_use_a_ext_therm_2_enable_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 therm_evt_ext_therm_0_r(void)
{
return 0x00020700;
return 0x00020700U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
{
return (v & 0x3f) << 8;
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_0_priority_f(u32 v)
{
return (v & 0x1f) << 24;
return (v & 0x1fU) << 24U;
}
static inline u32 therm_evt_ext_therm_1_r(void)
{
return 0x00020704;
return 0x00020704U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
{
return (v & 0x3f) << 8;
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_1_priority_f(u32 v)
{
return (v & 0x1f) << 24;
return (v & 0x1fU) << 24U;
}
static inline u32 therm_evt_ext_therm_2_r(void)
{
return 0x00020708;
return 0x00020708U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
{
return (v & 0x3f) << 8;
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_2_priority_f(u32 v)
{
return (v & 0x1f) << 24;
return (v & 0x1fU) << 24U;
}
static inline u32 therm_weight_1_r(void)
{
return 0x00020024;
return 0x00020024U;
}
static inline u32 therm_config1_r(void)
{
return 0x00020050;
return 0x00020050U;
}
static inline u32 therm_config2_r(void)
{
return 0x00020130;
return 0x00020130U;
}
static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
{
return (v & 0x1) << 24;
return (v & 0x1U) << 24U;
}
static inline u32 therm_config2_grad_enable_f(u32 v)
{
return (v & 0x1) << 31;
return (v & 0x1U) << 31U;
}
static inline u32 therm_gate_ctrl_r(u32 i)
{
return 0x00020200 + i*4;
return 0x00020200U + i*4U;
}
static inline u32 therm_gate_ctrl_eng_clk_m(void)
{
return 0x3 << 0;
return 0x3U << 0U;
}
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 therm_gate_ctrl_blk_clk_m(void)
{
return 0x3 << 2;
return 0x3U << 2U;
}
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
{
return 0x3 << 4;
return 0x3U << 4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
{
return 0x20;
return 0x20U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1f) << 8;
return (v & 0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return 0x1f << 8;
return 0x1fU << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7) << 13;
return (v & 0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return 0x7 << 13;
return 0x7U << 13U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
{
return (v & 0xf) << 16;
return (v & 0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
{
return 0xf << 16;
return 0xfU << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xf) << 20;
return (v & 0xfU) << 20U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return 0xf << 20;
return 0xfU << 20U;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288;
return 0x00020288U;
}
static inline u32 therm_fecs_idle_filter_value_m(void)
{
return 0xffffffff << 0;
return 0xffffffffU << 0U;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028c;
return 0x0002028cU;
}
static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return 0xffffffff << 0;
return 0xffffffffU << 0U;
}
static inline u32 therm_clk_slowdown_r(u32 i)
{
return 0x00020160 + i*4;
return 0x00020160U + i*4U;
}
static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
{
return (v & 0x3f) << 16;
return (v & 0x3fU) << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_m(void)
{
return 0x3f << 16;
return 0x3fU << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
{
return (r >> 16) & 0x3f;
return (r >> 16U) & 0x3fU;
}
static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 therm_grad_stepping_table_r(u32 i)
{
return 0x000202c8 + i*4;
return 0x000202c8U + i*4U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
{
return (v & 0x3f) << 0;
return (v & 0x3fU) << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
{
return 0x3f << 0;
return 0x3fU << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
{
return 0x2;
return 0x2U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
{
return 0x6;
return 0x6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
{
return 0xe;
return 0xeU;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
{
return (v & 0x3f) << 6;
return (v & 0x3fU) << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
{
return 0x3f << 6;
return 0x3fU << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
{
return (v & 0x3f) << 12;
return (v & 0x3fU) << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
{
return 0x3f << 12;
return 0x3fU << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
{
return (v & 0x3f) << 18;
return (v & 0x3fU) << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
{
return 0x3f << 18;
return 0x3fU << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
{
return (v & 0x3f) << 24;
return (v & 0x3fU) << 24U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
{
return 0x3f << 24;
return 0x3fU << 24U;
}
static inline u32 therm_grad_stepping0_r(void)
{
return 0x000202c0;
return 0x000202c0U;
}
static inline u32 therm_grad_stepping0_feature_s(void)
{
return 1;
return 1U;
}
static inline u32 therm_grad_stepping0_feature_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1U) << 0U;
}
static inline u32 therm_grad_stepping0_feature_m(void)
{
return 0x1 << 0;
return 0x1U << 0U;
}
static inline u32 therm_grad_stepping0_feature_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 therm_grad_stepping0_feature_enable_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 therm_grad_stepping1_r(void)
{
return 0x000202c4;
return 0x000202c4U;
}
static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
{
return (v & 0x1ffff) << 0;
return (v & 0x1ffffU) << 0U;
}
static inline u32 therm_clk_timing_r(u32 i)
{
return 0x000203c0 + i*4;
return 0x000203c0U + i*4U;
}
static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
{
return (v & 0x1) << 16;
return (v & 0x1U) << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_m(void)
{
return 0x1 << 16;
return 0x1U << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
{
return 0x10000;
return 0x10000U;
}
#endif

28
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
View File

@@ -58,58 +58,58 @@
static inline u32 timer_pri_timeout_r(void)
{
return 0x00009080;
return 0x00009080U;
}
static inline u32 timer_pri_timeout_period_f(u32 v)
{
return (v & 0xffffff) << 0;
return (v & 0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_m(void)
{
return 0xffffff << 0;
return 0xffffffU << 0U;
}
static inline u32 timer_pri_timeout_period_v(u32 r)
{
return (r >> 0) & 0xffffff;
return (r >> 0U) & 0xffffffU;
}
static inline u32 timer_pri_timeout_en_f(u32 v)
{
return (v & 0x1) << 31;
return (v & 0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_m(void)
{
return 0x1 << 31;
return 0x1U << 31U;
}
static inline u32 timer_pri_timeout_en_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_en_en_enabled_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 timer_pri_timeout_en_en_disabled_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084;
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088;
return 0x00009088U;
}
static inline u32 timer_pri_timeout_fecs_errcode_r(void)
{
return 0x0000908c;
return 0x0000908cU;
}
static inline u32 timer_time_0_r(void)
{
return 0x00009400;
return 0x00009400U;
}
static inline u32 timer_time_1_r(void)
{
return 0x00009410;
return 0x00009410U;
}
#endif

76
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h
View File

@@ -58,154 +58,154 @@
static inline u32 top_num_gpcs_r(void)
{
return 0x00022430;
return 0x00022430U;
}
static inline u32 top_num_gpcs_value_v(u32 r)
{
return (r >> 0) & 0x1f;
return (r >> 0U) & 0x1fU;
}
static inline u32 top_tpc_per_gpc_r(void)
{
return 0x00022434;
return 0x00022434U;
}
static inline u32 top_tpc_per_gpc_value_v(u32 r)
{
return (r >> 0) & 0x1f;
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbps_r(void)
{
return 0x00022438;
return 0x00022438U;
}
static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0) & 0x1f;
return (r >> 0U) & 0x1fU;
}
static inline u32 top_device_info_r(u32 i)
{
return 0x00022700 + i*4;
return 0x00022700U + i*4U;
}
static inline u32 top_device_info__size_1_v(void)
{
return 0x00000040;
return 0x00000040U;
}
static inline u32 top_device_info_chain_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 top_device_info_chain_enable_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 top_device_info_engine_enum_v(u32 r)
{
return (r >> 26) & 0xf;
return (r >> 26U) & 0xfU;
}
static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21) & 0xf;
return (r >> 21U) & 0xfU;
}
static inline u32 top_device_info_intr_enum_v(u32 r)
{
return (r >> 15) & 0x1f;
return (r >> 15U) & 0x1fU;
}
static inline u32 top_device_info_reset_enum_v(u32 r)
{
return (r >> 9) & 0x1f;
return (r >> 9U) & 0x1fU;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2) & 0x1fffffff;
return (r >> 2U) & 0x1fffffffU;
}
static inline u32 top_device_info_type_enum_graphics_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4;
return 0x4U;
}
static inline u32 top_device_info_type_enum_copy1_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 top_device_info_type_enum_copy1_f(void)
{
return 0x8;
return 0x8U;
}
static inline u32 top_device_info_type_enum_copy2_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 top_device_info_type_enum_copy2_f(void)
{
return 0xc;
return 0xcU;
}
static inline u32 top_device_info_engine_v(u32 r)
{
return (r >> 5) & 0x1;
return (r >> 5U) & 0x1U;
}
static inline u32 top_device_info_runlist_v(u32 r)
{
return (r >> 4) & 0x1;
return (r >> 4U) & 0x1U;
}
static inline u32 top_device_info_intr_v(u32 r)
{
return (r >> 3) & 0x1;
return (r >> 3U) & 0x1U;
}
static inline u32 top_device_info_reset_v(u32 r)
{
return (r >> 2) & 0x1;
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0) & 0x3;
return (r >> 0U) & 0x3U;
}
static inline u32 top_device_info_entry_not_valid_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002;
return 0x00000002U;
}
static inline u32 top_device_info_entry_engine_type_v(void)
{
return 0x00000003;
return 0x00000003U;
}
static inline u32 top_device_info_entry_data_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 top_fs_status_fbp_r(void)
{
return 0x00022548;
return 0x00022548U;
}
static inline u32 top_fs_status_fbp_cluster_v(u32 r)
{
return (r >> 0) & 0xffff;
return (r >> 0U) & 0xffffU;
}
static inline u32 top_fs_status_fbp_cluster_enable_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 top_fs_status_fbp_cluster_enable_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 top_fs_status_fbp_cluster_disable_v(void)
{
return 0x00000001;
return 0x00000001U;
}
static inline u32 top_fs_status_fbp_cluster_disable_f(void)
{
return 0x1;
return 0x1U;
}
#endif

128
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h
View File

@@ -58,258 +58,258 @@
static inline u32 trim_sys_gpcpll_cfg_r(void)
{
return 0x00137000;
return 0x00137000U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
{
return 0x1 << 0;
return 0x1U << 0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
{
return (r >> 0) & 0x1;
return (r >> 0U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
{
return 0x1 << 1;
return 0x1U << 1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
{
return 0x1 << 4;
return 0x1U << 4U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
{
return 0x10;
return 0x10U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
{
return (r >> 17) & 0x1;
return (r >> 17U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
{
return 0x20000;
return 0x20000U;
}
static inline u32 trim_sys_gpcpll_coeff_r(void)
{
return 0x00137004;
return 0x00137004U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
{
return 0xff << 0;
return 0xffU << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
{
return (r >> 0) & 0xff;
return (r >> 0U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
{
return (v & 0xff) << 8;
return (v & 0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
{
return 0xff << 8;
return 0xffU << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
{
return (r >> 8) & 0xff;
return (r >> 8U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
{
return (v & 0x3f) << 16;
return (v & 0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
{
return 0x3f << 16;
return 0x3fU << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
{
return (r >> 16) & 0x3f;
return (r >> 16U) & 0x3fU;
}
static inline u32 trim_sys_sel_vco_r(void)
{
return 0x00137100;
return 0x00137100U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
{
return 0x1 << 0;
return 0x1U << 0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
{
return 0x00000000;
return 0x00000000U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
{
return 0x1;
return 0x1U;
}
static inline u32 trim_sys_gpc2clk_out_r(void)
{
return 0x00137250;
return 0x00137250U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
{
return 6;
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
{
return (v & 0x3f) << 0;
return (v & 0x3fU) << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
{
return 0x3f << 0;
return 0x3fU << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
{
return (r >> 0) & 0x3f;
return (r >> 0U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
{
return 0x3c;
return 0x3cU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
{
return 6;
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
{
return (v & 0x3f) << 8;
return (v & 0x3fU) << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
{
return 0x3f << 8;
return 0x3fU << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
{
return (r >> 8) & 0x3f;
return (r >> 8U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
{
return 0x1 << 31;
return 0x1U << 31U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
{
return 0x00134124 + i*512;
return 0x00134124U + i*512U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
{
return (v & 0x3fff) << 0;
return (v & 0x3fffU) << 0U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
{
return 0x10000;
return 0x10000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
{
return 0x100000;
return 0x100000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
{
return 0x1000000;
return 0x1000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
{
return 0x00134128 + i*512;
return 0x00134128U + i*512U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
{
return (r >> 0) & 0xfffff;
return (r >> 0U) & 0xfffffU;
}
static inline u32 trim_sys_gpcpll_cfg2_r(void)
{
return 0x0013700c;
return 0x0013700cU;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
{
return (v & 0xff) << 24;
return (v & 0xffU) << 24U;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
{
return 0xff << 24;
return 0xffU << 24U;
}
static inline u32 trim_sys_gpcpll_cfg3_r(void)
{
return 0x00137018;
return 0x00137018U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
{
return (v & 0xff) << 16;
return (v & 0xffU) << 16U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
{
return 0xff << 16;
return 0xffU << 16U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
{
return 0x0013701c;
return 0x0013701cU;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
{
return 0x1 << 22;
return 0x1U << 22U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
{
return 0x400000;
return 0x400000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
{
return 0x1 << 31;
return 0x1U << 31U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
{
return 0x80000000;
return 0x80000000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
{
return 0x0;
return 0x0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
{
return 0x001328a0;
return 0x001328a0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
{
return (r >> 24) & 0x1;
return (r >> 24U) & 0x1U;
}
#endif