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gpu: nvgpu: channel MISRA fix for Rule 17.7

Browse Source 
Check return value of below function and add void to ignore
the return value
update_gp_get

Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count

JIRA NVGPU-3388

Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-09 10:33:22 -07:00
committed by mobile promotions
parent 766dfb2cb1
commit 334f855ac4
3 changed files with 15 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -1393,7 +1393,7 @@ void gk20a_channel_free_usermode_buffers(struct nvgpu_channel *c)
}
/* Update with this periodically to determine how the gpfifo is draining. */
static inline u32 update_gp_get(struct gk20a *g,
static inline u32 nvgpu_channel_update_gpfifo_get(struct gk20a *g,
struct nvgpu_channel *c)
{
u32 new_get = g->ops.userd.gp_get(g, c);
@@ -1402,10 +1402,10 @@ static inline u32 update_gp_get(struct gk20a *g,
return new_get;
}
u32 nvgpu_gp_free_count(struct nvgpu_channel *c)
u32 nvgpu_channel_get_gpfifo_free_count(struct nvgpu_channel *ch)
{
return (c->gpfifo.entry_num - (c->gpfifo.put - c->gpfifo.get) - 1U) %
c->gpfifo.entry_num;
return (ch->gpfifo.entry_num - (ch->gpfifo.put - ch->gpfifo.get) - 1U) %
ch->gpfifo.entry_num;
}
static bool nvgpu_channel_ctxsw_timeout_debug_dump_state(struct gk20a *g,
@@ -1463,7 +1463,7 @@ void nvgpu_channel_set_ctx_mmu_error(struct gk20a *g,
bool nvgpu_channel_update_and_check_ctxsw_timeout(struct nvgpu_channel *ch,
u32 timeout_delta_ms, bool *progress)
{
u32 gpfifo_get = update_gp_get(ch->g, ch);
u32 gpfifo_get = nvgpu_channel_update_gpfifo_get(ch->g, ch);
if (gpfifo_get == ch->ctxsw_timeout_gpfifo_get) {
/* didn't advance since previous ctxsw timeout check */
@@ -1481,10 +1481,10 @@ bool nvgpu_channel_update_and_check_ctxsw_timeout(struct nvgpu_channel *ch,
ch->ctxsw_timeout_accumulated_ms > ch->ctxsw_timeout_max_ms;
}
u32 nvgpu_get_gp_free_count(struct nvgpu_channel *c)
u32 nvgpu_channel_update_gpfifo_get_and_get_free_count(struct nvgpu_channel *ch)
{
update_gp_get(c->g, c);
return nvgpu_gp_free_count(c);
(void)nvgpu_channel_update_gpfifo_get(ch->g, ch);
return nvgpu_channel_get_gpfifo_free_count(ch);
}
static void nvgpu_channel_wdt_init(struct nvgpu_channel *ch)

6
drivers/gpu/nvgpu/common/fifo/submit.c
View File

@@ -504,8 +504,10 @@ static int nvgpu_submit_channel_gpfifo(struct nvgpu_channel *c,
* values first and then read from HW. If no space, return EAGAIN
* and let userpace decide to re-try request or not.
*/
if (nvgpu_gp_free_count(c) < num_entries + extra_entries) {
if (nvgpu_get_gp_free_count(c) < num_entries + extra_entries) {
if (nvgpu_channel_get_gpfifo_free_count(c) <
num_entries + extra_entries) {
if (nvgpu_channel_update_gpfifo_get_and_get_free_count(c) <
num_entries + extra_entries) {
err = -EAGAIN;
goto clean_up;
}

5
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -487,8 +487,9 @@ int channel_gk20a_alloc_job(struct nvgpu_channel *c,
struct nvgpu_channel_job **job_out);
void channel_gk20a_free_job(struct nvgpu_channel *c,
struct nvgpu_channel_job *job);
u32 nvgpu_get_gp_free_count(struct nvgpu_channel *c);
u32 nvgpu_gp_free_count(struct nvgpu_channel *c);
u32 nvgpu_channel_update_gpfifo_get_and_get_free_count(
struct nvgpu_channel *ch);
u32 nvgpu_channel_get_gpfifo_free_count(struct nvgpu_channel *ch);
int gk20a_channel_add_job(struct nvgpu_channel *c,
struct nvgpu_channel_job *job,
bool skip_buffer_refcounting);