From 33e9d08610adf51a52b0b01caf938cdbd8c9dc3b Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 14 Jan 2019 16:07:38 +0530 Subject: [PATCH] gpu: nvgpu: Modify dgpu WPR/NON-WPR address space Currently, there is free space of 3MB with current implementation due to gap between WPR & NON-WPR offset, with this PMU buffers are allocated between this space & some are after WPR. So, modified WPR to allocate at 0th offset of bootstrap-region of VIDMEM & NON-WPR to be at WPR+WPR_SIZE offset of bootstrap-region to make contiguous free space available till end of bootstrap-region of VIDMEM. Increased WPR/NON-WPR size from 1MB to 2MB as LS falcon managed count increased to 4 for Turing & remains 2MB for previous chips too. Bug 200476497 Change-Id: I92ca5bc9a571330d75a66ce820a1c82442c1f200 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1994653 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/acr_gp106.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gp106.c b/drivers/gpu/nvgpu/common/pmu/acr_gp106.c index 49b0f37ea..4a3eb14b9 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gp106.c @@ -54,10 +54,7 @@ typedef int (*gp106_get_ucode_details)(struct gk20a *g, struct flcn_ucode_img_v1 *udata); /* Both size and address of WPR need to be 128K-aligned */ -#define WPR_ALIGNMENT 0x20000U -#define GP106_DGPU_NONWPR NVGPU_VIDMEM_BOOTSTRAP_ALLOCATOR_BASE -#define GP106_DGPU_WPR_OFFSET 0x400000U -#define DGPU_WPR_SIZE 0x100000U +#define DGPU_WPR_SIZE 0x200000U /*Externs*/ @@ -73,8 +70,8 @@ static gp106_get_ucode_details pmu_acr_supp_ucode_list[] = { void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) { - inf->nonwpr_base = g->mm.vidmem.bootstrap_base; - inf->wpr_base = inf->nonwpr_base + GP106_DGPU_WPR_OFFSET; + inf->wpr_base = g->mm.vidmem.bootstrap_base; + inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE; inf->size = DGPU_WPR_SIZE; }