From 3407c01357e8041941011d4e5c7f1b7683e0201b Mon Sep 17 00:00:00 2001 From: Santosh BS Date: Mon, 22 May 2023 15:55:58 +0000 Subject: [PATCH] gpu: nvgpu: gops declaration for multimedia engines - gops struct declaration for nvenc, ofa, nvdec and nvjpg - minor refactoring with struct nvgpu_nvenc Jira NVGPU-9429 Bug 3962979 Change-Id: I888c6bd571554f18f2e9ca2adfaaacd1a8286ed0 Signed-off-by: Santosh BS Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2908521 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-common.yaml | 5 +- .../gpu/nvgpu/common/falcon/falcon_sw_tu104.c | 2 +- .../gpu/nvgpu/common/multimedia/multimedia.c | 1 - .../nvgpu/common/multimedia/multimedia_priv.h | 3 - drivers/gpu/nvgpu/common/multimedia/nvenc.c | 1 - .../nvgpu/common/multimedia/nvenc_bootstrap.h | 43 ----- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 2 +- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h | 143 ++++++++++++++- drivers/gpu/nvgpu/include/nvgpu/gops/nvenc.h | 91 +++++++++- drivers/gpu/nvgpu/include/nvgpu/gops/nvjpg.h | 168 ++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/gops/ofa.h | 168 ++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h | 8 +- drivers/gpu/nvgpu/include/nvgpu/multimedia.h | 2 + drivers/gpu/nvgpu/include/nvgpu/nvenc.h | 19 ++ 15 files changed, 593 insertions(+), 65 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/multimedia/nvenc_bootstrap.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gops/nvjpg.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gops/ofa.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index e9e24d221..22d102c4d 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -419,7 +419,9 @@ falcon: common/falcon/falcon_debug.h, include/nvgpu/gops/gsp.h, include/nvgpu/gops/nvdec.h, - include/nvgpu/gops/nvenc.h ] + include/nvgpu/gops/nvenc.h, + include/nvgpu/gops/ofa.h, + include/nvgpu/gops/nvjpg.h ] deps: [ ] tags: @@ -1190,7 +1192,6 @@ multimedia: owner: santosh B S gpu: both sources: [ common/multimedia/nvenc.c, - common/multimedia/nvenc_bootstrap.h, include/nvgpu/nvenc.h ] ## diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c index acb85f458..c93607ad0 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_tu104.c @@ -79,7 +79,7 @@ void tu104_falcon_sw_init(struct nvgpu_falcon *flcn) flcn->is_interrupt_enabled = true; break; case FALCON_ID_NVDEC: - flcn->flcn_base = g->ops.nvdec.falcon_base_addr(); + flcn->flcn_base = g->ops.nvdec.base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = true; break; diff --git a/drivers/gpu/nvgpu/common/multimedia/multimedia.c b/drivers/gpu/nvgpu/common/multimedia/multimedia.c index 779cdf9c0..137ba0117 100644 --- a/drivers/gpu/nvgpu/common/multimedia/multimedia.c +++ b/drivers/gpu/nvgpu/common/multimedia/multimedia.c @@ -37,7 +37,6 @@ #include #include #include "multimedia_priv.h" -#include "nvenc_bootstrap.h" /* Engine ctx buffer size. 256-byte aligned */ #define MULTIMEDIA_CTX_BUF_SIZE (4096U) diff --git a/drivers/gpu/nvgpu/common/multimedia/multimedia_priv.h b/drivers/gpu/nvgpu/common/multimedia/multimedia_priv.h index e39d560f1..5d2fe4632 100644 --- a/drivers/gpu/nvgpu/common/multimedia/multimedia_priv.h +++ b/drivers/gpu/nvgpu/common/multimedia/multimedia_priv.h @@ -25,9 +25,6 @@ #define TU104_NVENC_UCODE_FW "nvhost_nvenc072.fw" -#define MULTIMEDIA_UCODE_HEADER_SIZE (APP_0_CODE_SIZE + 1) -#define MULTIMEDIA_UCODE_HEADER_SIZE_BYTES (MULTIMEDIA_UCODE_HEADER_SIZE * 4) - struct multimedia_fw_hdr { /* 0x10de */ u32 fw_magic; diff --git a/drivers/gpu/nvgpu/common/multimedia/nvenc.c b/drivers/gpu/nvgpu/common/multimedia/nvenc.c index fb3bc735f..089b99541 100644 --- a/drivers/gpu/nvgpu/common/multimedia/nvenc.c +++ b/drivers/gpu/nvgpu/common/multimedia/nvenc.c @@ -34,7 +34,6 @@ #include #include #include "multimedia_priv.h" -#include "nvenc_bootstrap.h" /* NVENC init */ int nvgpu_nvenc_sw_init(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/multimedia/nvenc_bootstrap.h b/drivers/gpu/nvgpu/common/multimedia/nvenc_bootstrap.h deleted file mode 100644 index 77d942788..000000000 --- a/drivers/gpu/nvgpu/common/multimedia/nvenc_bootstrap.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVENC_BOOTSTRAP_H -#define NVENC_BOOTSTRAP_H - -/* NVENC core descriptor */ -struct nvgpu_nvenc { - - /* NVENC ucode */ - const char *fw_name; - - /* NVENC ucode header info */ - u32 ucode_header[MULTIMEDIA_UCODE_HEADER_SIZE]; - - /* Falcon used to execute NVENC ucode */ - struct nvgpu_falcon *nvenc_flcn; - - /** Memory to store ucode contents locally. */ - struct nvgpu_mem nvenc_mem_desc; - -}; - -#endif /* NVENC_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 129cae6c2..b87eca190 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -988,7 +988,7 @@ static const struct gops_fb ga100_ops_fb = { }; static const struct gops_nvdec ga100_ops_nvdec = { - .falcon_base_addr = ga100_nvdec_falcon_base_addr, + .base_addr = ga100_nvdec_falcon_base_addr, }; static const struct gops_cg ga100_ops_cg = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index b5ca00bc2..1b413bd11 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -887,7 +887,7 @@ static const struct gops_fb tu104_ops_fb = { }; static const struct gops_nvdec tu104_ops_nvdec = { - .falcon_base_addr = tu104_nvdec_falcon_base_addr, + .base_addr = tu104_nvdec_falcon_base_addr, }; static const struct gops_nvenc tu104_ops_nvenc = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h b/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h index 5832b1511..f9c64126d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -22,8 +22,147 @@ #ifndef NVGPU_GOPS_NVDEC_H #define NVGPU_GOPS_NVDEC_H +struct nvgpu_multimedia_ctx; + struct gops_nvdec { - u32 (*falcon_base_addr)(void); + + /** + * @brief Base address of NVDEC apperture. + * + * This function gets the base address of NVDEC aperture. + */ + u32 (*base_addr)(void); + + /** + * @brief falcon2 base address of NVDEC aperture. + * + * This function gets the falcon2 base address of NVDEC aperture. + */ + u32 (*falcon2_base_addr)(void); + + /** + * @brief Initialize NVDEC support. + * + * @param g [in] Pointer to GPU driver struct. + * + * Initializes the private data struct for NVDEC unit in the GPU driver + * according to the current chip. + */ + int (*init)(struct gk20a *g); + + /** + * @brief Deinitialize NVDEC support. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function frees the memory allocated during initialization. + */ + int (*deinit)(struct gk20a *g); + + /** + * @brief Reset NVDEC engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function resets the NVDEC HW unit and loads the firmware again. + */ + int (*reset)(struct gk20a *g); + + /** + * Load and bootstrap ucode on NVDEC falcon. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function takes care of loading the firmware. It kick-starts + * the core and polls for the successful initialization. + */ + int (*bootstrap)(struct gk20a *g); + + /** + * @brief Set-up boot configuration registers. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function programs the configuration registers needed before boot. + */ + void (*setup_boot_config)(struct gk20a *g); + + /** + * @brief Halt the engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function halts the engine. + */ + void (*halt_engine)(struct gk20a *g); + + /** + * @brief Configure interrupt registers. + * + * @param g [in] Pointer to GPU driver struct. + * @param flcn [in] Pointer to falcon struct. + * + * This function programs the interrupt configuration registers. + */ + void (*set_irq_regs)(struct gk20a *g, struct nvgpu_falcon *flcn); + + /** + * @brief Enable interrupts for NVDEC. + * + * @param g [in] Pointer to GPU driver struct. + * @param enable [in] Parameter to enable/disable interrupt. + * + * This function enables/disables the interrupts for NVDEC as requested. + */ + void (*enable_irq)(struct gk20a *g, bool enable); + + /** + * @brief Enable interfaces (method or ctx switch) for NVDEC. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function enables method and/or ctx switch interfaces for NVDEC. + */ + void (*interface_enable)(struct gk20a *g); + + /** + * @brief Interrupt handler for NVDEC interrupts. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function handles the interrupts from NVDEC and takes the necessary + * actions. + */ + void (*nvdec_isr)(struct gk20a *g); + + /** + * @brief Allocate and setup engine context for GPU channel. + * + * @param ch [in] Pointer to GPU channel. + * @param class_num [in] GPU class ID. + * @param flags [in] Flags for context allocation. + * + * This HAL allocates and sets up engine context for + * a GPU channel. + * + * @return 0 in case of success, < 0 in case of failure. + * @retval -ENOMEM if memory allocation for context buffer fails. + * @retval -EINVAL if invalid GPU class ID is provided. + */ + int (*multimedia_alloc_ctx)(struct nvgpu_channel *ch, + u32 class_num, u32 flags); + + /** + * @brief Free engine context buffer. + * + * @param g [in] Pointer to GPU driver struct. + * @param eng_ctx [in] Pointer to engine context data. + * + * This function frees the memory allocated for engine + * context buffer. + */ + void (*multimedia_free_ctx)(struct gk20a *g, + struct nvgpu_multimedia_ctx *eng_ctx); }; #endif /* NVGPU_GOPS_NVDEC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/nvenc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/nvenc.h index 2e0150d02..687c7d62d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/nvenc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/nvenc.h @@ -26,10 +26,27 @@ struct nvgpu_multimedia_ctx; struct gops_nvenc { - u32 (*base_addr)(void); /** - * Initializes nvenc unit private data struct in the GPU driver based on - * the current chip. + * @brief Base address of NVENC apperture. + * + * This function gets the base address of NVENC aperture. + */ + u32 (*base_addr)(void); + + /** + * @brief falcon2 base address of NVENC aperture. + * + * This function gets the falcon2 base address of NVENC aperture. + */ + u32 (*falcon2_base_addr)(void); + + /** + * @brief Initialize NVENC support. + * + * @param g [in] Pointer to GPU driver struct. + * + * Initializes the private data struct for NVENC unit in the GPU driver + * according to the current chip. */ int (*init)(struct gk20a *g); @@ -38,28 +55,86 @@ struct gops_nvenc { * * @param g [in] Pointer to GPU driver struct. * - * This function de-allocates memory allocated during initialization. + * This function frees the memory allocated during initialization. */ int (*deinit)(struct gk20a *g); /** - * @brief Reset NVENC. + * @brief Reset NVENC engine. * * @param g [in] Pointer to GPU driver struct. * - * This function resets the NVENC HW unit and loads the FW again. + * This function resets the NVENC HW unit and loads the firmware again. */ int (*reset)(struct gk20a *g); /** - * Load and bootstrap ucode on nvenc falcon. + * Load and bootstrap ucode on NVENC falcon. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function takes care of loading the firmware. It kick-starts + * the core and polls for the successful initialization. */ int (*bootstrap)(struct gk20a *g); + + /** + * @brief Set-up boot configuration registers. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function programs the configuration registers needed before boot. + */ void (*setup_boot_config)(struct gk20a *g); + + /** + * @brief Halt the engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function halts the engine. + */ void (*halt_engine)(struct gk20a *g); + + /** + * @brief Configure interrupt registers. + * + * @param g [in] Pointer to GPU driver struct. + * @param flcn [in] Pointer to falcon struct. + * + * This function programs the interrupt configuration registers. + */ void (*set_irq_regs)(struct gk20a *g, struct nvgpu_falcon *flcn); + + /** + * @brief Enable interrupts for NVENC. + * + * @param g [in] Pointer to GPU driver struct. + * @param enable [in] Parameter to enable/disable interrupt. + * + * This function enables/disables the interrupts for NVENC as requested. + */ + void (*enable_irq)(struct gk20a *g, bool enable); + + /** + * @brief Enable interfaces (method or ctx switch) for NVENC. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function enables method and/or ctx switch interfaces for NVENC. + */ void (*interface_enable)(struct gk20a *g); + /** + * @brief Interrupt handler for NVENC interrupts. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function handles the interrupts from NVENC and takes the necessary + * actions. + */ + void (*nvenc_isr)(struct gk20a *g); + /** * @brief Allocate and setup engine context for GPU channel. * @@ -83,7 +158,7 @@ struct gops_nvenc { * @param g [in] Pointer to GPU driver struct. * @param eng_ctx [in] Pointer to engine context data. * - * This function will free the memory allocated for engine + * This function frees the memory allocated for engine * context buffer. */ void (*multimedia_free_ctx)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/nvjpg.h b/drivers/gpu/nvgpu/include/nvgpu/gops/nvjpg.h new file mode 100644 index 000000000..98313f1d2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/nvjpg.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_NVJPG_H +#define NVGPU_GOPS_NVJPG_H + +struct nvgpu_multimedia_ctx; + +struct gops_nvjpg { + + /** + * @brief Base address of NVJPG apperture. + * + * This function gets the base address of NVJPG aperture. + */ + u32 (*base_addr)(void); + + /** + * @brief falcon2 base address of NVJPG aperture. + * + * This function gets the falcon2 base address of NVJPG aperture. + */ + u32 (*falcon2_base_addr)(void); + + /** + * @brief Initialize NVJPG support. + * + * @param g [in] Pointer to GPU driver struct. + * + * Initializes the private data struct for NVJPG unit in the GPU driver + * according to the current chip. + */ + int (*init)(struct gk20a *g); + + /** + * @brief Deinitialize NVJPG support. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function frees the memory allocated during initialization. + */ + int (*deinit)(struct gk20a *g); + + /** + * @brief Reset NVJPG engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function resets the NVJPG HW unit and loads the firmware again. + */ + int (*reset)(struct gk20a *g); + + /** + * Load and bootstrap ucode on NVJPG falcon. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function takes care of loading the firmware. It kick-starts + * the core and polls for the successful initialization. + */ + int (*bootstrap)(struct gk20a *g); + + /** + * @brief Set-up boot configuration registers. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function programs the configuration registers needed before boot. + */ + void (*setup_boot_config)(struct gk20a *g); + + /** + * @brief Halt the engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function halts the engine. + */ + void (*halt_engine)(struct gk20a *g); + + /** + * @brief Configure interrupt registers. + * + * @param g [in] Pointer to GPU driver struct. + * @param flcn [in] Pointer to falcon struct. + * + * This function programs the interrupt configuration registers. + */ + void (*set_irq_regs)(struct gk20a *g, struct nvgpu_falcon *flcn); + + /** + * @brief Enable interrupts for NVJPG. + * + * @param g [in] Pointer to GPU driver struct. + * @param enable [in] Parameter to enable/disable interrupt. + * + * This function enables/disables the interrupts for NVJPG as requested. + */ + void (*enable_irq)(struct gk20a *g, bool enable); + + /** + * @brief Enable interfaces (method or ctx switch) for NVJPG. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function enables method and/or ctx switch interfaces for NVJPG. + */ + void (*interface_enable)(struct gk20a *g); + + /** + * @brief Interrupt handler for NVJPG interrupts. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function handles the interrupts from NVJPG and takes the necessary + * actions. + */ + void (*nvjpg_isr)(struct gk20a *g); + + /** + * @brief Allocate and setup engine context for GPU channel. + * + * @param ch [in] Pointer to GPU channel. + * @param class_num [in] GPU class ID. + * @param flags [in] Flags for context allocation. + * + * This HAL allocates and sets up engine context for + * a GPU channel. + * + * @return 0 in case of success, < 0 in case of failure. + * @retval -ENOMEM if memory allocation for context buffer fails. + * @retval -EINVAL if invalid GPU class ID is provided. + */ + int (*multimedia_alloc_ctx)(struct nvgpu_channel *ch, + u32 class_num, u32 flags); + + /** + * @brief Free engine context buffer. + * + * @param g [in] Pointer to GPU driver struct. + * @param eng_ctx [in] Pointer to engine context data. + * + * This function frees the memory allocated for engine + * context buffer. + */ + void (*multimedia_free_ctx)(struct gk20a *g, + struct nvgpu_multimedia_ctx *eng_ctx); +}; + +#endif /* NVGPU_GOPS_NVJPG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ofa.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ofa.h new file mode 100644 index 000000000..0fb39839b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ofa.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_OFA_H +#define NVGPU_GOPS_OFA_H + +struct nvgpu_multimedia_ctx; + +struct gops_ofa { + + /** + * @brief Base address of OFA apperture. + * + * This function gets the base address of OFA aperture. + */ + u32 (*base_addr)(void); + + /** + * @brief falcon2 base address of OFA aperture. + * + * This function gets the falcon2 base address of OFA aperture. + */ + u32 (*falcon2_base_addr)(void); + + /** + * @brief Initialize OFA support. + * + * @param g [in] Pointer to GPU driver struct. + * + * Initializes the private data struct for OFA unit in the GPU driver + * according to the current chip. + */ + int (*init)(struct gk20a *g); + + /** + * @brief Deinitialize OFA support. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function frees the memory allocated during initialization. + */ + int (*deinit)(struct gk20a *g); + + /** + * @brief Reset OFA engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function resets the OFA HW unit and loads the firmware again. + */ + int (*reset)(struct gk20a *g); + + /** + * Load and bootstrap ucode on OFA falcon. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function takes care of loading the firmware. It kick-starts + * the core and polls for the successful initialization. + */ + int (*bootstrap)(struct gk20a *g); + + /** + * @brief Set-up boot configuration registers. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function programs the configuration registers needed before boot. + */ + void (*setup_boot_config)(struct gk20a *g); + + /** + * @brief Halt the engine. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function halts the engine. + */ + void (*halt_engine)(struct gk20a *g); + + /** + * @brief Configure interrupt registers. + * + * @param g [in] Pointer to GPU driver struct. + * @param flcn [in] Pointer to falcon struct. + * + * This function programs the interrupt configuration registers. + */ + void (*set_irq_regs)(struct gk20a *g, struct nvgpu_falcon *flcn); + + /** + * @brief Enable interrupts for OFA. + * + * @param g [in] Pointer to GPU driver struct. + * @param enable [in] Parameter to enable/disable interrupt. + * + * This function enables/disables the interrupts for OFA as requested. + */ + void (*enable_irq)(struct gk20a *g, bool enable); + + /** + * @brief Enable interfaces (method or ctx switch) for OFA. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function enables method and/or ctx switch interfaces for OFA. + */ + void (*interface_enable)(struct gk20a *g); + + /** + * @brief Interrupt handler for OFA interrupts. + * + * @param g [in] Pointer to GPU driver struct. + * + * This function handles the interrupts from OFA and takes the necessary + * actions. + */ + void (*ofa_isr)(struct gk20a *g); + + /** + * @brief Allocate and setup engine context for GPU channel. + * + * @param ch [in] Pointer to GPU channel. + * @param class_num [in] GPU class ID. + * @param flags [in] Flags for context allocation. + * + * This HAL allocates and sets up engine context for + * a GPU channel. + * + * @return 0 in case of success, < 0 in case of failure. + * @retval -ENOMEM if memory allocation for context buffer fails. + * @retval -EINVAL if invalid GPU class ID is provided. + */ + int (*multimedia_alloc_ctx)(struct nvgpu_channel *ch, + u32 class_num, u32 flags); + + /** + * @brief Free engine context buffer. + * + * @param g [in] Pointer to GPU driver struct. + * @param eng_ctx [in] Pointer to engine context data. + * + * This function frees the memory allocated for engine + * context buffer. + */ + void (*multimedia_free_ctx)(struct gk20a *g, + struct nvgpu_multimedia_ctx *eng_ctx); +}; + +#endif /* NVGPU_GOPS_OFA_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h b/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h index e3e4feb82..c69b40fb2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h @@ -33,8 +33,10 @@ #include #include #include -#include #include +#include +#include +#include #include #include #include @@ -238,8 +240,10 @@ struct gpu_ops { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ struct gops_sbr sbr; struct gops_func func; - struct gops_nvdec nvdec; struct gops_nvenc nvenc; + struct gops_ofa ofa; + struct gops_nvdec nvdec; + struct gops_nvjpg nvjpg; struct gops_ramfc ramfc; struct gops_ramin ramin; struct gops_userd userd; diff --git a/drivers/gpu/nvgpu/include/nvgpu/multimedia.h b/drivers/gpu/nvgpu/include/nvgpu/multimedia.h index 1f7fe2e60..79317b059 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/multimedia.h +++ b/drivers/gpu/nvgpu/include/nvgpu/multimedia.h @@ -26,6 +26,8 @@ #include #define UCODE_DMA_ID (0x6) +#define MULTIMEDIA_UCODE_HEADER_SIZE (APP_0_CODE_SIZE + 1) +#define MULTIMEDIA_UCODE_HEADER_SIZE_BYTES (MULTIMEDIA_UCODE_HEADER_SIZE * 4) struct nvgpu_tsg; struct vm_gk20a; diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvenc.h b/drivers/gpu/nvgpu/include/nvgpu/nvenc.h index bcba226ab..254a524f1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvenc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvenc.h @@ -23,6 +23,25 @@ #ifndef NVGPU_NVENC_H #define NVGPU_NVENC_H +#include + +/* NVENC core descriptor */ +struct nvgpu_nvenc { + + /* NVENC ucode */ + const char *fw_name; + + /* NVENC ucode header info */ + u32 ucode_header[MULTIMEDIA_UCODE_HEADER_SIZE]; + + /* Falcon used to execute NVENC ucode */ + struct nvgpu_falcon *nvenc_flcn; + + /** Memory to store ucode contents locally. */ + struct nvgpu_mem nvenc_mem_desc; + +}; + struct gk20a; int nvgpu_nvenc_falcon_boot(struct gk20a *g);