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gpu: nvgpu: remove channel debug_dump hal

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Channel debug_dump hal function does not involve
any register related code.

Move gv11b_channel_debug_dump hal function to
common code nvgpu_channel_info_debug_dump function.

Check gpu hw version to limit instance variables
dump that differs between socs.

Add new hal pointer syncpt_debug_dump for pbdma.

Jira NVGPU-5109

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2020-03-30 18:07:27 -07:00
committed by Alex Waterman
parent 62c06723dd
commit 340ea241cb
13 changed files with 94 additions and 112 deletions
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84
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -2844,6 +2844,88 @@ void nvgpu_channel_free_inst(struct gk20a *g, struct nvgpu_channel *ch)
nvgpu_free_inst_block(g, &ch->inst_block);
}
static void nvgpu_channel_sync_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o, struct nvgpu_channel_dump_info *info)
{
#ifdef CONFIG_NVGPU_NON_FUSA
gk20a_debug_output(o,
"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
"FETCH: %016llx"
"HEADER: %08x COUNT: %08x"
"SYNCPOINT: %08x %08x "
"SEMAPHORE: %08x %08x %08x %08x",
info->inst.pb_top_level_get,
info->inst.pb_put,
info->inst.pb_get,
info->inst.pb_fetch,
info->inst.pb_header,
info->inst.pb_count,
info->inst.syncpointa,
info->inst.syncpointb,
info->inst.semaphorea,
info->inst.semaphoreb,
info->inst.semaphorec,
info->inst.semaphored);
g->ops.pbdma.syncpt_debug_dump(g, o, info);
#endif
}
static void nvgpu_channel_info_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info)
{
/**
* Use gpu hw version to control the channel instance fields
* dump in nvgpu_channel_dump_info struct.
* For hw version before gv11b, dump syncpoint a/b, semaphore a/b/c/d.
* For hw version after gv11b, dump sem addr/payload/execute.
*/
u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl);
gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",
info->chid,
g->name,
info->tsgid,
info->pid,
info->refs,
info->deterministic ? ", deterministic" : "");
gk20a_debug_output(o, "channel status: %s in use %s %s",
info->hw_state.enabled ? "" : "not",
info->hw_state.status_string,
info->hw_state.busy ? "busy" : "not busy");
if (ver < NVGPU_GPUID_GV11B) {
nvgpu_channel_sync_debug_dump(g, o, info);
} else {
gk20a_debug_output(o,
"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
"FETCH: %016llx"
"HEADER: %08x COUNT: %08x"
"SEMAPHORE: addr %016llx"
"payload %016llx execute %08x",
info->inst.pb_top_level_get,
info->inst.pb_put,
info->inst.pb_get,
info->inst.pb_fetch,
info->inst.pb_header,
info->inst.pb_count,
info->inst.sem_addr,
info->inst.sem_payload,
info->inst.sem_execute);
}
if (info->sema.addr != 0ULL) {
gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
"next_val: 0x%08x addr: 0x%010llx",
info->sema.value,
info->sema.next,
info->sema.addr);
}
gk20a_debug_output(o, "\n");
}
void nvgpu_channel_debug_dump_all(struct gk20a *g,
struct nvgpu_debug_context *o)
{
@@ -2916,7 +2998,7 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
struct nvgpu_channel_dump_info *info = infos[chid];
if (info != NULL) {
g->ops.channel.debug_dump(g, o, info);
nvgpu_channel_info_debug_dump(g, o, info);
nvgpu_kfree(g, info);
}
}

53
drivers/gpu/nvgpu/hal/fifo/channel_gk20a.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,8 +28,6 @@
#include <nvgpu/bug.h>
#include <nvgpu/gk20a.h>
#include "hal/fifo/pbdma_gm20b.h"
#include "channel_gk20a.h"
#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
@@ -46,52 +44,3 @@ void gk20a_channel_unbind(struct nvgpu_channel *ch)
ccsr_channel_inst_bind_false_f());
}
}
void gk20a_channel_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info)
{
gk20a_debug_output(o, "Channel ID: %d, TSG ID: %u, pid %d, refs %d; "
"deterministic = %s",
info->chid,
info->tsgid,
info->pid,
info->refs,
info->deterministic ? "yes" : "no");
gk20a_debug_output(o, " In use: %-3s busy: %-3s status: %s",
info->hw_state.enabled ? "yes" : "no",
info->hw_state.busy ? "yes" : "no",
info->hw_state.status_string);
gk20a_debug_output(o,
" TOP %016llx"
" PUT %016llx GET %016llx",
info->inst.pb_top_level_get,
info->inst.pb_put,
info->inst.pb_get);
gk20a_debug_output(o,
" FETCH %016llx"
" HEADER %08x COUNT %08x",
info->inst.pb_fetch,
info->inst.pb_header,
info->inst.pb_count);
gk20a_debug_output(o,
" SYNCPOINT %08x %08x "
"SEMAPHORE %08x %08x %08x %08x",
info->inst.syncpointa,
info->inst.syncpointb,
info->inst.semaphorea,
info->inst.semaphoreb,
info->inst.semaphorec,
info->inst.semaphored);
if (info->sema.addr == 0ULL) {
gk20a_debug_output(o,
" SEMA STATE: val: %u next_val: %u addr: 0x%010llx",
info->sema.value,
info->sema.next,
info->sema.addr);
}
gm20b_pbdma_syncpoint_debug_dump(g, o, info);
gk20a_debug_output(o, " ");
}

7
drivers/gpu/nvgpu/hal/fifo/channel_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,6 @@ struct gk20a;
struct nvgpu_channel;
struct nvgpu_channel_hw_state;
struct nvgpu_debug_context;
struct nvgpu_channel_dump_info;
void gv11b_channel_unbind(struct nvgpu_channel *ch);
u32 gv11b_channel_count(struct gk20a *g);
@@ -37,8 +36,4 @@ void gv11b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
struct nvgpu_channel_hw_state *state);
void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
bool eng, bool pbdma);
void gv11b_channel_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info);
#endif /* FIFO_CHANNEL_GV11B_H */

42
drivers/gpu/nvgpu/hal/fifo/channel_gv11b_fusa.c
View File

@@ -80,45 +80,3 @@ void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
nvgpu_writel(g, ccsr_channel_r(ch->chid), reg);
}
void gv11b_channel_debug_dump(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info)
{
gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",
info->chid,
g->name,
info->tsgid,
info->pid,
info->refs,
info->deterministic ? ", deterministic" : "");
gk20a_debug_output(o, "channel status: %s in use %s %s\n",
info->hw_state.enabled ? "" : "not",
info->hw_state.status_string,
info->hw_state.busy ? "busy" : "not busy");
gk20a_debug_output(o,
"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
"FETCH: %016llx\n"
"HEADER: %08x COUNT: %08x\n"
"SEMAPHORE: addr %016llx\n"
"payload %016llx execute %08x\n",
info->inst.pb_top_level_get,
info->inst.pb_put,
info->inst.pb_get,
info->inst.pb_fetch,
info->inst.pb_header,
info->inst.pb_count,
info->inst.sem_addr,
info->inst.sem_payload,
info->inst.sem_execute);
if (info->sema.addr != 0ULL) {
gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
"next_val: 0x%08x addr: 0x%010llx\n",
info->sema.value,
info->sema.next,
info->sema.addr);
}
gk20a_debug_output(o, "\n");
}

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -692,6 +692,7 @@ static const struct gpu_ops gm20b_ops = {
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gm20b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.syncpt_debug_dump = gm20b_pbdma_syncpoint_debug_dump,
.handle_intr_0 = gm20b_pbdma_handle_intr_0,
.handle_intr_1 = gm20b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
@@ -812,7 +813,6 @@ static const struct gpu_ops gm20b_ops = {
.resume_all_serviceable_ch =
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier,
.debug_dump = gk20a_channel_debug_dump,
},
.tsg = {
.enable = gk20a_tsg_enable,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -780,6 +780,7 @@ static const struct gpu_ops gp10b_ops = {
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.syncpt_debug_dump = gm20b_pbdma_syncpoint_debug_dump,
.handle_intr_0 = gm20b_pbdma_handle_intr_0,
.handle_intr_1 = gm20b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
@@ -917,7 +918,6 @@ static const struct gpu_ops gp10b_ops = {
.resume_all_serviceable_ch =
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier,
.debug_dump = gk20a_channel_debug_dump,
},
.tsg = {
.enable = gk20a_tsg_enable,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -983,6 +983,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.syncpt_debug_dump = NULL,
.dump_status = gm20b_pbdma_dump_status,
#endif
.handle_intr_0 = gv11b_pbdma_handle_intr_0,
@@ -1117,7 +1118,6 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier_if_empty,
.reset_faulted = gv11b_channel_reset_faulted,
.debug_dump = gv11b_channel_debug_dump,
},
.tsg = {
.enable = gv11b_tsg_enable,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1008,6 +1008,7 @@ static const struct gpu_ops tu104_ops = {
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.syncpt_debug_dump = NULL,
.dump_status = gm20b_pbdma_dump_status,
#endif
.handle_intr = gm20b_pbdma_handle_intr,
@@ -1141,7 +1142,6 @@ static const struct gpu_ops tu104_ops = {
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier_if_empty,
.reset_faulted = gv11b_channel_reset_faulted,
.debug_dump = gv11b_channel_debug_dump,
},
.tsg = {
.enable = gv11b_tsg_enable,

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
View File

@@ -609,7 +609,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.resume_all_serviceable_ch =
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier,
.debug_dump = NULL,
},
.tsg = {
.open = vgpu_tsg_open,

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -729,7 +729,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.resume_all_serviceable_ch =
nvgpu_channel_resume_all_serviceable_ch,
.set_error_notifier = nvgpu_set_err_notifier,
.debug_dump = NULL,
},
.tsg = {
.open = vgpu_tsg_open,

2
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -187,7 +187,7 @@ struct nvgpu_channel_dump_info {
bool deterministic;
/** Channel H/W state */
struct nvgpu_channel_hw_state hw_state;
/** Snaphsot of channel instance fields. */
/** Snapshot of channel instance fields. */
struct {
u64 pb_top_level_get;
u64 pb_put;

4
drivers/gpu/nvgpu/include/nvgpu/gops_channel.h
View File

@@ -33,7 +33,6 @@ struct gk20a;
struct nvgpu_channel;
struct nvgpu_channel_hw_state;
struct nvgpu_debug_context;
struct nvgpu_channel_dump_info;
/**
* Channel HAL operations.
@@ -142,9 +141,6 @@ struct gops_channel {
void (*abort_clean_up)(struct nvgpu_channel *ch);
void (*reset_faulted)(struct gk20a *g, struct nvgpu_channel *ch,
bool eng, bool pbdma);
void (*debug_dump)(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info);
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
int (*set_syncpt)(struct nvgpu_channel *ch);

4
drivers/gpu/nvgpu/include/nvgpu/gops_pbdma.h
View File

@@ -32,6 +32,7 @@ struct nvgpu_pbdma_status_info;
/** NON FUSA */
struct nvgpu_debug_context;
struct nvgpu_channel_dump_info;
struct gops_pbdma_status {
void (*read_pbdma_status_info)(struct gk20a *g,
@@ -84,6 +85,9 @@ struct gops_pbdma {
u32 (*allowed_syncpoints_0_index_v)(u32 offset);
/** NON FUSA */
void (*syncpt_debug_dump)(struct gk20a *g,
struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info);
void (*dump_status)(struct gk20a *g,
struct nvgpu_debug_context *o);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)