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gpu: nvgpu: vgpu: merge tegra_vgpu_t18x.h to tegra_vgpu.h

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No need to keep two vgpu headers anymore.

Jira VFND-3796

Change-Id: I400cbfa5b2c0e62963eff247adcd9483be975379
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1457480
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2017-04-06 17:32:14 -07:00
committed by mobile promotions
parent 14959cf682
commit 3429657f93
3 changed files with 18 additions and 52 deletions
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3
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
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@@ -117,9 +117,6 @@ static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
&msg.params.gr_bind_ctxsw_buffers; &msg.params.gr_bind_ctxsw_buffers;
int err = 0; int err = 0;
WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX !=
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST);
if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;

25
include/linux/tegra_vgpu.h
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@@ -19,10 +19,6 @@
#ifndef __TEGRA_VGPU_H #ifndef __TEGRA_VGPU_H
#define __TEGRA_VGPU_H #define __TEGRA_VGPU_H
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
#include <linux/tegra_vgpu_t18x.h>
#endif
enum { enum {
TEGRA_VGPU_MODULE_GPU = 0, TEGRA_VGPU_MODULE_GPU = 0,
}; };
@@ -139,6 +135,7 @@ enum {
TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */ TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */ TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64, /* gap to hide T18x IP */
}; };
struct tegra_vgpu_attrib_params { struct tegra_vgpu_attrib_params {
@@ -281,12 +278,26 @@ struct tegra_vgpu_zbc_query_table_params {
u32 index_size; /* [out] size, [in] index */ u32 index_size; /* [out] size, [in] index */
}; };
#define TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX 4 enum {
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST
};
enum {
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST
};
struct tegra_vgpu_gr_bind_ctxsw_buffers_params { struct tegra_vgpu_gr_bind_ctxsw_buffers_params {
u64 handle; /* deprecated */ u64 handle; /* deprecated */
u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST];
u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST];
u32 mode; u32 mode;
u64 gr_ctx_handle; u64 gr_ctx_handle;
}; };

42
include/linux/tegra_vgpu_t18x.h
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@@ -1,42 +0,0 @@
/*
* Tegra GPU Virtualization Interfaces to Server
*
* Copyright (c) 2015, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __TEGRA_VGPU_T18X_H
#define __TEGRA_VGPU_T18X_H
enum {
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB,
TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST
};
enum {
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP,
TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST
};
enum {
TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64
};
#endif