From 344eceb7391df40f49d47037560cd8375b90939e Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 12 Jun 2019 13:27:48 -0700 Subject: [PATCH] gpu: nvgpu: fix CERT-C issues in ltc intr driver Use nvgpu_safe_add_u32 for u32 additions in ltc interrupt driver. JIRA NVGPU-3623 Change-Id: If4d1b126836c5980e7016ed42b588b435f4f7f66 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2135322 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c | 4 ++-- drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c | 11 ++++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c index b7ee37efe..c02bb53cb 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c @@ -79,8 +79,8 @@ void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice) "Double bit error detected in GPU L2!"); ecc_stats_reg_val = - nvgpu_readl(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset); + nvgpu_readl(g, nvgpu_safe_add_u32( + ltc_ltc0_lts0_dstg_ecc_report_r(), offset)); g->ecc.ltc.ecc_ded_count[ltc][slice].counter = nvgpu_safe_add_u32( g->ecc.ltc.ecc_ded_count[ltc][slice].counter, diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c index 32da405f6..91fff2b22 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c @@ -154,9 +154,14 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); } - g->ecc.ltc.ecc_sec_count[ltc][slice].counter += corrected_delta; - g->ecc.ltc.ecc_ded_count[ltc][slice].counter += - uncorrected_delta; + g->ecc.ltc.ecc_sec_count[ltc][slice].counter = + nvgpu_safe_add_u32( + g->ecc.ltc.ecc_sec_count[ltc][slice].counter, + corrected_delta); + g->ecc.ltc.ecc_ded_count[ltc][slice].counter = + nvgpu_safe_add_u32( + g->ecc.ltc.ecc_ded_count[ltc][slice].counter, + uncorrected_delta); nvgpu_log(g, gpu_dbg_intr, "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3);