nvgpu: gpu: Support multiple tpc-pg masks.

- TPC powergating should be done before
  calling gk20a_enable_gr_hw.
  gk20a_enable_gr_hw() issues a GR engine reset.

  Without this fix, enabling 1 TPC from each PES
  causes ctxsw timeout error while running GFX Benchmark.

- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
    TPC Config - TPC-MASK
  4 TPC configuration - 0x0
  3 TPC configuration - 0x1/0x2/0x4/0x8
  2 TPC configuration - 0x5/0x9/0x6/0xa

- We should not write to gr_fe_tpc_pesmask_r()
  as part of TPC-PG sequence. This register is for
  debug purpose only.

Bug 200442360

Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/os/linux/platform_gk20a.h

@@ -74,7 +74,7 @@ struct gk20a_platform {
 	struct reset_control *reset_control;
 #endif
 	/* valid TPC-MASK */
-	u32 valid_tpc_mask;
+	u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
 
 	/* Delay before rail gated */
 	int railgate_delay_init;