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nvgpu: gpu: Support multiple tpc-pg masks.

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- TPC powergating should be done before
  calling gk20a_enable_gr_hw.
  gk20a_enable_gr_hw() issues a GR engine reset.

  Without this fix, enabling 1 TPC from each PES
  causes ctxsw timeout error while running GFX Benchmark.

- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
    TPC Config - TPC-MASK
  4 TPC configuration - 0x0
  3 TPC configuration - 0x1/0x2/0x4/0x8
  2 TPC configuration - 0x5/0x9/0x6/0xa

- We should not write to gr_fe_tpc_pesmask_r()
  as part of TPC-PG sequence. This register is for
  debug purpose only.

Bug 200442360

Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Goyal
2018-09-14 11:45:19 +05:30
committed by mobile promotions
parent 991179f29c
commit 34732a14b2
7 changed files with 47 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/os/linux/sysfs.c
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@@ -865,6 +865,18 @@ static ssize_t tpc_pg_mask_read(struct device *dev,
return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask);
}
static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask)
{
u32 i;
bool valid = false;
for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
if (tpc_mask == g->valid_tpc_mask[i])
valid = true;
}
return valid;
}
static ssize_t tpc_pg_mask_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
@@ -896,10 +908,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
return -ENODEV;
}
if (val == TPC_MASK_FOR_ALL_ACTIVE_TPCs || val == g->valid_tpc_mask) {
if (is_tpc_mask_valid(g, (u32)val)) {
g->tpc_pg_mask = val;
} else {
nvgpu_err(g, "TPC-PG mask is invalid");
nvgpu_mutex_release(&g->tpc_pg_lock);
return -EINVAL;