gpu: nvgpu: fix MISRA 17.7 in falcon_bootstrap

MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.

JIRA NVGPU-677

Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fb/fb_gv100.c

@@ -214,7 +214,11 @@ int gv100_fb_memory_unlock(struct gk20a *g)
 		FALCON_MAILBOX_0, 0xdeadbeefU);
 
 	/* set BOOTVEC to start of non-secure code */
-	nvgpu_falcon_bootstrap(g->nvdec_flcn, 0);
+	err = nvgpu_falcon_bootstrap(g->nvdec_flcn, 0);
+	if (err != 0) {
+		nvgpu_err(g, "falcon bootstrap failed %d", err);
+		goto exit;
+	}
 
 	/* wait for complete & halt */
 	nvgpu_falcon_wait_for_halt(g->nvdec_flcn, MEM_UNLOCK_TIMEOUT);

drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c

@@ -120,9 +120,9 @@ static bool gv100_nvlink_minion_is_running(struct gk20a *g)
 /*
  * Load minion FW and set up bootstrap
  */
-static u32 gv100_nvlink_minion_load(struct gk20a *g)
+static int gv100_nvlink_minion_load(struct gk20a *g)
 {
-	u32 err = 0;
+	int err = 0;
 	struct nvgpu_firmware *nvgpu_minion_fw = NULL;
 	struct nvgpu_timeout timeout;
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
@@ -154,7 +154,10 @@ static u32 gv100_nvlink_minion_load(struct gk20a *g)
 	}
 
 	/* set BOOTVEC to start of non-secure code */
-	nvgpu_falcon_bootstrap(g->minion_flcn, 0x0);
+	err = nvgpu_falcon_bootstrap(g->minion_flcn, 0x0);
+	if (err != 0) {
+		goto exit;
+	}
 
 	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
 		NVGPU_TIMER_CPU_TIMER);
@@ -462,7 +465,7 @@ static u32 gv100_nvlink_get_link_reset_mask(struct gk20a *g)
 	return ioctrl_reset_linkreset_v(reg_data);
 }
 
-static u32 gv100_nvlink_state_load_hal(struct gk20a *g)
+static int gv100_nvlink_state_load_hal(struct gk20a *g)
 {
 	unsigned long discovered = g->nvlink.discovered_links;
 

drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c

@@ -191,6 +191,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu)
 		(struct pmu_ucode_desc *)(void *)pmu->fw_image->data;
 	u64 addr_code, addr_data, addr_load;
 	u32 i, blocks, addr_args;
+	int err;
 
 	nvgpu_log_fn(g, " ");
 
@@ -264,11 +265,11 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu)
 			pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE));
 	}
 
-	nvgpu_falcon_bootstrap(g->pmu.flcn, desc->bootloader_entry_point);
+	err = nvgpu_falcon_bootstrap(g->pmu.flcn, desc->bootloader_entry_point);
 
 	gk20a_writel(g, pwr_falcon_os_r(), desc->app_version);
 
-	return 0;
+	return err;
 }
 
 void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id)

drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c

@@ -363,9 +363,7 @@ static int gm20b_bl_bootstrap(struct gk20a *g,
 		  pwr_pmu_new_instblk_target_sys_coh_f() :
 		  pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
 
-	nvgpu_falcon_bl_bootstrap(g->pmu.flcn, bl_info);
-
-	return 0;
+	return nvgpu_falcon_bl_bootstrap(g->pmu.flcn, bl_info);
 }
 
 int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,

drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c

@@ -207,6 +207,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
 	u64 addr_code_lo, addr_data_lo, addr_load_lo;
 	u64 addr_code_hi, addr_data_hi;
 	u32 i, blocks, addr_args;
+	int err;
 
 	nvgpu_log_fn(g, " ");
 
@@ -302,11 +303,11 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
 			pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE));
 	}
 
-	nvgpu_falcon_bootstrap(pmu->flcn, desc->bootloader_entry_point);
+	err = nvgpu_falcon_bootstrap(pmu->flcn, desc->bootloader_entry_point);
 
 	gk20a_writel(g, pwr_falcon_os_r(), desc->app_version);
 
-	return 0;
+	return err;
 }
 
 void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0)

drivers/gpu/nvgpu/gp106/bios_gp106.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -107,7 +107,12 @@ int gp106_bios_devinit(struct gk20a *g)
 			g->bios.bootscripts_size,
 			0);
 
-	nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point);
+	err = nvgpu_falcon_bootstrap(g->pmu.flcn,
+					g->bios.devinit.code_entry_point);
+	if (err != 0) {
+		nvgpu_err(g, "falcon bootstrap failed %d", err);
+		goto out;
+	}
 
 	nvgpu_timeout_init(g, &timeout,
 			   PMU_BOOT_TIMEOUT_MAX /
@@ -167,7 +172,12 @@ int gp106_bios_preos(struct gk20a *g)
 			g->bios.preos.dmem_size,
 			0);
 
-	nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
+	err = nvgpu_falcon_bootstrap(g->pmu.flcn,
+					g->bios.preos.code_entry_point);
+	if (err != 0) {
+		nvgpu_err(g, "falcon bootstrap failed %d", err);
+		goto out;
+	}
 
 	err = g->ops.bios.preos_wait_for_halt(g);
 

drivers/gpu/nvgpu/include/nvgpu/nvlink.h

@@ -244,7 +244,7 @@ int nvgpu_nvlink_set_sublink_mode(struct gk20a *g,
 int nvgpu_nvlink_enumerate(struct gk20a *g);
 int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off);
 int nvgpu_nvlink_remove(struct gk20a *g);
-u32 nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
+int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
 					struct nvgpu_firmware *nvgpu_minion_fw);
 void nvgpu_mss_nvlink_init_credits(struct gk20a *g);
 

drivers/gpu/nvgpu/os/linux/nvlink.c

@@ -72,10 +72,10 @@ void nvgpu_nvlink_free_minion_used_mem(struct gk20a *g,
 /*
  * Load minion FW
  */
-u32 nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
+int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
 					struct nvgpu_firmware *nvgpu_minion_fw)
 {
-	u32 err = 0;
+	int err = 0;
 	struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
 	struct minion_hdr *minion_hdr = &ndev->minion_hdr;
 	u32 data_idx = 0;

drivers/gpu/nvgpu/os/posix/posix-nvlink.c

@@ -79,7 +79,7 @@ int nvgpu_nvlink_read_dt_props(struct gk20a *g)
 	return 0;
 }
 
-u32 nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
+int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
 					struct nvgpu_firmware *nvgpu_minion_fw)
 {
 	BUG();