From 34c24873a7928d58ec86620db3c684ce795280f8 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 25 Aug 2020 12:29:30 +0530 Subject: [PATCH] gpu: nvgpu: trigger gpc reset from common.gr GPC reset is right now triggered from common.mc unit for NVGPU_NEXT. Move the triggers to common code in common.gr unit. This way it is much more cleaner to handle multiple GR instances (added in subsequent patch) Hardcode GR engine instance to 0 for now since by default there is only one GR engine instance. Jira NVGPU-5648 Change-Id: I3fd4d0a50db5a8c4b3decf1df881af323cea50c1 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2403549 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index c15c8e096..a9c94f436 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -611,12 +611,28 @@ static int gr_init_prepare_hw(struct gk20a *g) #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT) int err; - if (g->ops.mc.reset_engine != NULL) { + if (g->ops.gr.init.reset_gpcs != NULL) { + const struct nvgpu_device *dev = + nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS, 0); + g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); - err = nvgpu_next_mc_reset_engine(g, NVGPU_DEVTYPE_GRAPHICS); + err = g->ops.mc.reset_engine_enable(g, dev->reset_id, false); if (err != 0) { - nvgpu_err(g, "NVGPU_ENGINE_GR reset failed"); + nvgpu_err(g, "GR reset disable failed"); + return err; + } + + err = g->ops.gr.init.reset_gpcs(g); + if (err != 0) { + nvgpu_err(g, "GR reset GPCs failed"); + g->ops.mc.reset_engine_enable(g, dev->reset_id, true); + return err; + } + + err = g->ops.mc.reset_engine_enable(g, dev->reset_id, true); + if (err != 0) { + nvgpu_err(g, "GR reset enable failed"); return err; } } else {