diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c index e558c12d8..a4ca3a069 100644 --- a/drivers/gpu/nvgpu/gv100/bios_gv100.c +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c @@ -31,24 +31,24 @@ #include -#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ -#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ +#define PMU_BOOT_TIMEOUT_DEFAULT 100U /* usec */ +#define PMU_BOOT_TIMEOUT_MAX 2000000U /* usec */ -#define SCRATCH_PREOS_PROGRESS 6 -#define PREOS_PROGRESS_MASK(r) (((r) >> 12) & 0xf) -#define PREOS_PROGRESS_NOT_STARTED 0 -#define PREOS_PROGRESS_STARTED 1 -#define PREOS_PROGRESS_EXIT 2 -#define PREOS_PROGRESS_EXIT_SECUREMODE 3 -#define PREOS_PROGRESS_ABORTED 6 +#define SCRATCH_PREOS_PROGRESS 6U +#define PREOS_PROGRESS_MASK(r) (((r) >> 12U) & 0xfU) +#define PREOS_PROGRESS_NOT_STARTED 0U +#define PREOS_PROGRESS_STARTED 1U +#define PREOS_PROGRESS_EXIT 2U +#define PREOS_PROGRESS_EXIT_SECUREMODE 3U +#define PREOS_PROGRESS_ABORTED 6U -#define SCRATCH_PMU_EXIT_AND_HALT 1 -#define PMU_EXIT_AND_HALT_SET(r, v) (((r) & ~0x200UL) | (v)) -#define PMU_EXIT_AND_HALT_YES (0x1UL << 9) +#define SCRATCH_PMU_EXIT_AND_HALT 1U +#define PMU_EXIT_AND_HALT_SET(r, v) (((r) & ~0x200U) | (v)) +#define PMU_EXIT_AND_HALT_YES BIT32(9) -#define SCRATCH_PRE_OS_RELOAD 1 -#define PRE_OS_RELOAD_SET(r, v) (((r) & ~0x100UL) | (v)) -#define PRE_OS_RELOAD_YES (0x1UL << 8) +#define SCRATCH_PRE_OS_RELOAD 1U +#define PRE_OS_RELOAD_SET(r, v) (((r) & ~0x100U) | (v)) +#define PRE_OS_RELOAD_YES BIT32(8) void gv100_bios_preos_reload_check(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index 0b5515f26..c66347cfa 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c @@ -41,14 +41,14 @@ u32 gv100_fifo_get_num_fifos(struct gk20a *g) u32 gv100_fifo_get_preempt_timeout(struct gk20a *g) { - return g->fifo_eng_timeout_us / 1000 ; + return g->fifo_eng_timeout_us / 1000U; } void gv100_apply_ctxsw_timeout_intr(struct gk20a *g) { u32 timeout; - timeout = g->ch_wdt_timeout_ms*1000; + timeout = g->ch_wdt_timeout_ms*1000U; timeout = scale_ptimer(timeout, ptimer_scalingfactor10x(g->ptimer_src_freq)); timeout |= fifo_eng_timeout_detection_enabled_f(); diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 0f93c5701..cfa3f2761 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -51,13 +51,13 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, { struct gr_gk20a *gr = &g->gr; int err = 0; - u32 scale_factor = 512UL; /* Use fx23.9 */ - u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */ - u32 world_scale = 1024UL; /* World performance in [19:10] */ - u32 tpc_scale = 1; /* TPC balancing in [9:0] */ - u32 scg_num_pes = 0; + u32 scale_factor = 512U; /* Use fx23.9 */ + u32 pix_scale = 1024U*1024U; /* Pix perf in [29:20] */ + u32 world_scale = 1024U; /* World performance in [19:10] */ + u32 tpc_scale = 1U; /* TPC balancing in [9:0] */ + u32 scg_num_pes = 0U; u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */ - u32 average_tpcs = 0; /* Average of # of TPCs per GPC */ + u32 average_tpcs = 0U; /* Average of # of TPCs per GPC */ u32 deviation; /* absolute diff between TPC# and * average_tpcs, averaged across GPCs */ @@ -70,7 +70,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, int diff; bool is_tpc_removed_gpc = false; bool is_tpc_removed_pes = false; - u32 max_tpc_gpc = 0; + u32 max_tpc_gpc = 0U; u32 num_tpc_mask; u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) * nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); @@ -91,7 +91,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, goto free_resources; } /* Remove logical TPC from set */ - num_tpc_mask &= ~(0x1 << disable_tpc_id); + num_tpc_mask &= ~(BIT32(disable_tpc_id)); is_tpc_removed_gpc = true; } @@ -128,7 +128,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, err = -EINVAL; goto free_resources; } - num_tpc_mask &= ~(0x1 << disable_tpc_id); + num_tpc_mask &= ~(BIT32(disable_tpc_id)); is_tpc_removed_pes = true; } if (hweight32(num_tpc_mask) != 0UL) { @@ -142,7 +142,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, goto free_resources; } - if (max_tpc_gpc == 0) { + if (max_tpc_gpc == 0U) { *perf = 0; goto free_resources; } @@ -156,7 +156,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, if (diff < 0) { diff = -diff; } - deviation += diff; + deviation += U32(diff); } deviation /= gr->gpc_count; @@ -262,7 +262,7 @@ int gr_gv100_init_sm_id_table(struct gk20a *g) } } } - gpc_tpc_mask[gpc_table[gtpc]] &= ~(0x1 << tpc_table[gtpc]); + gpc_tpc_mask[gpc_table[gtpc]] &= ~(BIT64(tpc_table[gtpc])); } for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { @@ -307,13 +307,13 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) * Update PE table contents * for PE table, each patch buffer update writes 32 TPCs */ - size += DIV_ROUND_UP(gr->tpc_count, 32); + size += DIV_ROUND_UP(gr->tpc_count, 32U); /* * Update the PL table contents * For PL table, each patch buffer update configures 4 TPCs */ - size += DIV_ROUND_UP(gr->tpc_count, 4); + size += DIV_ROUND_UP(gr->tpc_count, 4U); /* * We need this for all subcontexts @@ -325,7 +325,7 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) * reserve two slots since DYNAMIC -> STATIC requires * DYNAMIC -> NONE -> STATIC */ - size += 2; + size += 2U; /* * Add current patch buffer size @@ -340,7 +340,7 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) /* * Increase the size to accommodate for additional TPC partition update */ - size += 2 * PATCH_CTX_SLOTS_PER_PAGE; + size += 2U * PATCH_CTX_SLOTS_PER_PAGE; return size; } @@ -361,7 +361,7 @@ static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g) */ active_fbpa_mask = g->ops.fuse.fuse_status_opt_fbio(g); active_fbpa_mask = ~active_fbpa_mask; - active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1); + active_fbpa_mask = active_fbpa_mask & (BIT32(num_fbpas) - 1U); return active_fbpa_mask; } @@ -392,7 +392,7 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, (regs->l[idx].addr & mask) + (fbpa_id * stride); map[cnt++].offset = off; - off += 4; + off += 4U; } } } diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h index 115e7ab32..217726582 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h @@ -25,14 +25,14 @@ #include -#define NV_PMU_THERM_CMD_ID_RPC 0x00000002 -#define NV_PMU_THERM_MSG_ID_RPC 0x00000002 -#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000 -#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 -#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 -#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001 -#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001 -#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001 +#define NV_PMU_THERM_CMD_ID_RPC 0x00000002U +#define NV_PMU_THERM_MSG_ID_RPC 0x00000002U +#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000U +#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006U +#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004U +#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001U +#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001U +#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001U struct nv_pmu_therm_rpc_slct_event_temp_th_set { s32 temp_threshold; diff --git a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h index 891991350..0f6acca4d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h @@ -33,7 +33,7 @@ struct nvgpu_cpu_time_correlation_sample { /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. 32 ns is the resolution of ptimer. */ -#define PTIMER_REF_FREQ_HZ 31250000 +#define PTIMER_REF_FREQ_HZ 31250000U static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) { @@ -42,10 +42,10 @@ static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) static inline u32 scale_ptimer(u32 timeout , u32 scale10x) { - if (((timeout*10) % scale10x) >= (scale10x/2)) { - return ((timeout * 10) / scale10x) + 1; + if (((timeout*10U) % scale10x) >= (scale10x/2U)) { + return ((timeout * 10U) / scale10x) + 1U; } else { - return (timeout * 10) / scale10x; + return (timeout * 10U) / scale10x; } } diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index 16afa4cde..2975aded3 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c @@ -273,7 +273,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), &ack_status, 1); - if (ack_status == 0) { + if (ack_status == 0U) { status = -EINVAL; nvgpu_err(g, "MCLK-CHANGE ACK failed"); } @@ -306,7 +306,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g) pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), &ack_status, 1); - if (ack_status == 0) { + if (ack_status == 0U) { status = -EINVAL; nvgpu_err(g, "post-init ack failed"); } diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h index b31a47287..9c0a123f6 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.h +++ b/drivers/gpu/nvgpu/lpwr/lpwr.h @@ -22,19 +22,19 @@ #ifndef NVGPU_LPWR_H #define NVGPU_LPWR_H -#define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 +#define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540U -#define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT(0x1) -#define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT(0x3) +#define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT32(0x1) +#define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT32(0x3) -#define LPWR_ENTRY_COUNT_MAX 0x06 +#define LPWR_ENTRY_COUNT_MAX 0x06U #define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) #define LPWR_VBIOS_IDX_ENTRY_RSVD \ - (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1) + (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1U) -#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500) +#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500U) struct nvgpu_lpwr_bios_idx_entry { u8 pcie_idx; diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index 03a24ed69..02da21507 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c @@ -91,7 +91,7 @@ static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) { pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), &success, 1); - if (success == 0) { + if (success == 0U) { status = -EINVAL; nvgpu_err(g, "Ack for the parameter command %x", prppg_cmd->cmn.cmd_id); diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index ed672a56c..1408163df 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c @@ -267,7 +267,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) if (g->ops.clk.support_clk_freq_domain) { err = nvgpu_clk_freq_domain_pmu_setup(g); - if (err != 0) { + if (err != 0U) { return err; } } @@ -393,7 +393,7 @@ static int parse_pstate_entry_5x(struct gk20a *g, (void) memset(pstate, 0, sizeof(struct pstate)); pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X; - pstate->num = 0x0F - entry->pstate_level; + pstate->num = 0x0FU - U32(entry->pstate_level); pstate->clklist.num_info = hdr->clock_entry_count; pstate->lpwr_entry_idx = entry->lpwr_entry_idx; @@ -443,7 +443,7 @@ static int parse_pstate_table_5x(struct gk20a *g, int err = 0; if ((hdr->header_size != VBIOS_PSTATE_HEADER_5X_SIZE_10) || - (hdr->base_entry_count == 0) || + (hdr->base_entry_count == 0U) || ((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) && (hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3) && (hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_6X_SIZE_5)) || diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h index abb72f497..f00591a4e 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/pstate/pstate.h @@ -26,13 +26,13 @@ #include "clk/clk.h" -#define CTRL_PERF_PSTATE_TYPE_3X 0x3 +#define CTRL_PERF_PSTATE_TYPE_3X 0x3U -#define CTRL_PERF_PSTATE_P0 0 -#define CTRL_PERF_PSTATE_P5 5 -#define CTRL_PERF_PSTATE_P8 8 +#define CTRL_PERF_PSTATE_P0 0U +#define CTRL_PERF_PSTATE_P5 5U +#define CTRL_PERF_PSTATE_P8 8U -#define CLK_SET_INFO_MAX_SIZE (32) +#define CLK_SET_INFO_MAX_SIZE (32U) struct gk20a; diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c index 99104333a..fa0f13b3c 100644 --- a/drivers/gpu/nvgpu/therm/thrmchannel.c +++ b/drivers/gpu/nvgpu/therm/thrmchannel.c @@ -112,7 +112,7 @@ static int _therm_channel_pmudata_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c index 0d26b438f..1cecb0cb0 100644 --- a/drivers/gpu/nvgpu/therm/thrmdev.c +++ b/drivers/gpu/nvgpu/therm/thrmdev.c @@ -45,7 +45,7 @@ static int _therm_device_pmudata_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index 5de770785..09716b090 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c @@ -111,7 +111,7 @@ static int therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, gk20a_get_gr_idle_timeout(g), &handlerparams->success, 1); - if (handlerparams->success == 0) { + if (handlerparams->success == 0U) { nvgpu_err(g, "could not process cmd"); status = -ETIMEDOUT; goto exit;