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gpu: nvgpu: Add compression for safety

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This is adding compression support for qnx-safety by
- Adding the compression related files under FUSA.
- Adding new posix contig-pool.c for user space compilation.

Bug 3426194

Change-Id: Ib3c8e587409dc12099c1196f55a87858d4dc520e
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2652963
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Dinesh T
2022-01-11 15:22:44 +00:00
committed by mobile promotions
parent 4b4ee3802a
commit 358f62a9d7
22 changed files with 330 additions and 315 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/nvgpu-hal-new.yaml
View File

@@ -471,10 +471,6 @@ mm:
hal/mm/cache/flush_gk20a.h,
hal/mm/cache/flush_gv11b_fusa.c,
hal/mm/cache/flush_gv11b.h ]
cache:
safe: no
sources: [ hal/mm/cache/flush_gk20a.c ]
mmu_fault:
safe: yes
sources: [ hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c,
@@ -804,6 +800,8 @@ fb_fusa:
hal/fb/fb_gm20b.h,
hal/fb/fb_gv11b_fusa.c,
hal/fb/fb_gv11b.h,
hal/fb/fb_gp10b_fusa.c, hal/fb/fb_gp10b.h,
hal/fb/fb_tu104_fusa.c, hal/fb/fb_tu104.h,
hal/fb/ecc/fb_ecc_gv11b.h, hal/fb/ecc/fb_ecc_gv11b_fusa.c,
hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c,
hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c,
@@ -824,10 +822,8 @@ fb:
owner: Seshendra G
sources: [ hal/fb/fb_gm20b.c,
hal/fb/fb_gp106.c, hal/fb/fb_gp106.h,
hal/fb/fb_gp10b.c, hal/fb/fb_gp10b.h,
hal/fb/fb_gv100.c, hal/fb/fb_gv100.h,
hal/fb/fb_gv11b.c,
hal/fb/fb_tu104.c, hal/fb/fb_tu104.h,
hal/fb/fb_tu104.c,
hal/fb/intr/fb_intr_gv100.h, hal/fb/intr/fb_intr_gv100.c,
hal/fb/fb_mmu_fault_tu104.h, hal/fb/fb_mmu_fault_tu104.c,
hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h,

5
arch/nvgpu-posix.yaml
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2019-2021, NVIDIA CORPORATION. All Rights Reserved.
# Copyright (c) 2019-2022, NVIDIA CORPORATION. All Rights Reserved.
#
# POSIX elements and units in nvgpu.
#
@@ -35,7 +35,8 @@ all:
os/posix/fecs_trace_posix.c,
os/posix/stubs.c,
os/posix/posix-vpr.c,
os/posix/mock-registers.c ]
os/posix/mock-registers.c,
os/posix/contig_pool.c ]
headers:
safe: no

5
drivers/gpu/nvgpu/Makefile
View File

@@ -382,9 +382,7 @@ nvgpu-y += \
hal/ltc/intr/ltc_intr_gm20b.o \
hal/ltc/intr/ltc_intr_gp10b.o \
hal/fb/fb_gm20b.o \
hal/fb/fb_gp10b.o \
hal/fb/fb_gp106.o \
hal/fb/fb_gv11b.o \
hal/fb/intr/fb_intr_ecc_gv11b.o \
hal/fuse/fuse_gm20b.o \
hal/fifo/fifo_gk20a.o \
@@ -736,6 +734,8 @@ nvgpu-y += \
hal/falcon/falcon_gk20a_fusa.o \
hal/fb/fb_gm20b_fusa.o \
hal/fb/fb_gv11b_fusa.o \
hal/fb/fb_gp10b_fusa.o \
hal/fb/fb_tu104_fusa.o \
hal/fb/fb_mmu_fault_gv11b_fusa.o \
hal/fb/ecc/fb_ecc_gv11b_fusa.o \
hal/fb/intr/fb_intr_ecc_gv11b_fusa.o \
@@ -827,7 +827,6 @@ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
hal/ltc/ltc_gm20b.o \
hal/ltc/ltc_gm20b_dbg.o \
hal/mc/mc_gm20b.o \
hal/mm/cache/flush_gk20a.o \
hal/mm/mm_gm20b.o \
hal/mm/mm_gk20a.o \
hal/mm/gmmu/gmmu_gk20a.o \

5
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -86,6 +86,8 @@ ifneq ($(NV_BUILD_CONFIGURATION_IS_VM_SERVER), 1)
CONFIG_NVGPU_ENABLE_MISC_EC := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_ENABLE_MISC_EC
endif
CONFIG_NVGPU_COMPRESSION := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_COMPRESSION
ifeq ($(profile),$(filter $(profile),safety_debug safety_release))
@@ -244,9 +246,6 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_POWER_PG
CONFIG_NVGPU_SIM := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SIM
CONFIG_NVGPU_COMPRESSION := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_COMPRESSION
# Enable non FUSA HALs for normal build
CONFIG_NVGPU_HAL_NON_FUSA := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_HAL_NON_FUSA

18
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -38,7 +38,8 @@ srcs += os/posix/nvgpu.c \
os/posix/posix-nvhost.c \
os/posix/posix-vgpu.c \
os/posix/posix-dt.c \
os/posix/fuse.c
os/posix/fuse.c \
os/posix/contig_pool.c
ifdef CONFIG_NVGPU_VPR
srcs += os/posix/posix-vpr.c
@@ -219,6 +220,8 @@ srcs += hal/mm/mm_gv11b_fusa.c \
hal/falcon/falcon_gk20a_fusa.c \
hal/fb/fb_gm20b_fusa.c \
hal/fb/fb_gv11b_fusa.c \
hal/fb/fb_gp10b_fusa.c \
hal/fb/fb_tu104_fusa.c \
hal/fb/fb_mmu_fault_gv11b_fusa.c \
hal/fb/ecc/fb_ecc_gv11b_fusa.c \
hal/fb/intr/fb_intr_ecc_gv11b_fusa.c \
@@ -287,12 +290,15 @@ srcs += hal/mm/mm_gv11b_fusa.c \
hal/cic/mon/init_ga10b_fusa.c \
hal/cic/mon/lut_ga10b_fusa.c
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += hal/cbc/cbc_tu104.c
endif
# Source files below are not guaranteed to be functionaly safe (FuSa) and are
# only included in the normal build.
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
srcs += hal/init/hal_gm20b.c \
hal/init/hal_gm20b_litter.c \
hal/mm/cache/flush_gk20a.c \
hal/mm/mm_gm20b.c \
hal/mm/mm_gk20a.c \
hal/mm/gmmu/gmmu_gk20a.c \
@@ -322,10 +328,8 @@ srcs += hal/init/hal_gm20b.c \
hal/ltc/ltc_gp10b.c \
hal/ltc/intr/ltc_intr_gm20b.c \
hal/ltc/intr/ltc_intr_gp10b.c \
hal/fb/fb_gp10b.c \
hal/fb/fb_gp106.c \
hal/fb/fb_gm20b.c \
hal/fb/fb_gv11b.c \
hal/fb/intr/fb_intr_ecc_gv11b.c \
hal/fuse/fuse_gm20b.c \
hal/fifo/fifo_gk20a.c \
@@ -641,9 +645,11 @@ srcs += common/mm/comptags.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c
ifeq ($(CONFIG_NVGPU_IVM_BUILD),1)
ifndef NVGPU_POSIX
srcs += common/cbc/contig_pool.c
endif
endif
endif
ifeq ($(CONFIG_NVGPU_REMAP),1)
srcs += common/mm/vm_remap.c
@@ -731,10 +737,6 @@ srcs += common/sec2/sec2.c \
hal/xve/xve_tu104.c
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += hal/cbc/cbc_tu104.c
endif
srcs += hal/gr/init/gr_init_tu104.c \
hal/class/class_tu104.c \
hal/mc/mc_tu104.c \

7
drivers/gpu/nvgpu/common/cbc/cbc.c
View File

@@ -117,9 +117,7 @@ static int nvgpu_init_cbc_mem(struct gk20a *g, u64 pa, u64 size)
return err;
}
static int nvgpu_get_mem_from_contigpool(struct gk20a *g,
size_t size,
struct nvgpu_mem *mem)
static int nvgpu_get_mem_from_contigpool(struct gk20a *g, size_t size)
{
struct nvgpu_contig_cbcmempool *contig_pool;
u64 pa;
@@ -181,8 +179,7 @@ int nvgpu_cbc_alloc(struct gk20a *g, size_t compbit_backing_size,
}
return nvgpu_get_mem_from_contigpool(g,
compbit_backing_size,
&cbc->compbit_store.mem);
compbit_backing_size);
} else
#endif
{

7
drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c
View File

@@ -73,13 +73,15 @@ int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
nvgpu_readl(g, ltc_ltcs_ltss_cbc_param_r()));
u64 base_divisor = 0ULL;
/* check if vidmem is present */
bool alloc_vidmem = g->ops.fb.get_vidmem_size != NULL ? true : false;
bool alloc_vidmem = false;
int err;
nvgpu_log_fn(g, " ");
#ifdef CONFIG_NVGPU_DGPU
alloc_vidmem = g->ops.fb.get_vidmem_size != NULL ? true : false;
#endif
if (max_comptag_lines == 0U) {
return 0;
}
@@ -171,5 +173,6 @@ int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
bool ga10b_cbc_use_contig_pool(struct gk20a *g)
{
(void)g;
return true;
}

31
drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
View File

@@ -61,37 +61,6 @@ void gm20b_fb_set_mmu_page_size(struct gk20a *g)
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
}
#ifdef CONFIG_NVGPU_COMPRESSION
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
{
/* set large page size in fb */
u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
return true;
}
u64 gm20b_fb_compression_page_size(struct gk20a *g)
{
(void)g;
return SZ_128K;
}
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g)
{
(void)g;
return (unsigned int)SZ_64K;
}
u64 gm20b_fb_compression_align_mask(struct gk20a *g)
{
(void)g;
return SZ_64K - 1UL;
}
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
{

33
drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B GPC MMU
*
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -283,3 +283,34 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size)
*wpr_base = wpr_start;
*wpr_size = nvgpu_safe_sub_u64(wpr_end, wpr_start);
}
#ifdef CONFIG_NVGPU_COMPRESSION
bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
{
/* set large page size in fb */
u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
return true;
}
u64 gm20b_fb_compression_page_size(struct gk20a *g)
{
(void)g;
return SZ_128K;
}
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g)
{
(void)g;
return (unsigned int)SZ_64K;
}
u64 gm20b_fb_compression_align_mask(struct gk20a *g)
{
(void)g;
return SZ_64K - 1UL;
}
#endif

2
drivers/gpu/nvgpu/hal/fb/fb_gp10b.c → drivers/gpu/nvgpu/hal/fb/fb_gp10b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B FB
*
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

103
drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
View File

@@ -1,103 +0,0 @@
/*
* GV11B FB
*
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/dma.h>
#include <nvgpu/log.h>
#include <nvgpu/enabled.h>
#include <nvgpu/gmmu.h>
#include <nvgpu/barrier.h>
#include <nvgpu/bug.h>
#include <nvgpu/soc.h>
#include <nvgpu/ptimer.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/timers.h>
#include <nvgpu/fifo.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/ltc.h>
#include <nvgpu/rc.h>
#include <nvgpu/engines.h>
#include "fb_gm20b.h"
#include "fb_gp10b.h"
#include "fb_gv11b.h"
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#ifdef CONFIG_NVGPU_COMPRESSION
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u32 compbit_base_post_divide;
u64 compbit_base_post_multiply64;
u64 compbit_store_iova;
u64 compbit_base_post_divide64;
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
compbit_store_iova = nvgpu_mem_get_phys_addr(g,
&cbc->compbit_store.mem);
} else
#endif
{
compbit_store_iova = nvgpu_mem_get_addr(g,
&cbc->compbit_store.mem);
}
/* must be aligned to 64 KB */
compbit_store_iova = round_up(compbit_store_iova, (u64)SZ_64K);
compbit_base_post_divide64 = compbit_store_iova >>
fb_mmu_cbc_base_address_alignment_shift_v();
do_div(compbit_base_post_divide64, nvgpu_ltc_get_ltc_count(g));
compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
nvgpu_ltc_get_ltc_count(g))
<< fb_mmu_cbc_base_address_alignment_shift_v();
if (compbit_base_post_multiply64 < compbit_store_iova) {
compbit_base_post_divide++;
}
if (g->ops.cbc.fix_config != NULL) {
compbit_base_post_divide =
g->ops.cbc.fix_config(g, (int)compbit_base_post_divide);
}
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(compbit_base_post_divide));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
(u32)(compbit_store_iova >> 32),
(u32)(compbit_store_iova & U32_MAX),
compbit_base_post_divide);
nvgpu_log(g, gpu_dbg_fn, "cbc base %x",
nvgpu_readl(g, fb_mmu_cbc_base_r()));
cbc->compbit_store.base_hw = compbit_base_post_divide;
}
#endif

55
drivers/gpu/nvgpu/hal/fb/fb_gv11b_fusa.c
View File

@@ -116,3 +116,58 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
nvgpu_writel(g, fb_priv_mmu_phy_secure_r(), U32_MAX);
}
}
#ifdef CONFIG_NVGPU_COMPRESSION
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u32 compbit_base_post_divide;
u64 compbit_base_post_multiply64;
u64 compbit_store_iova;
u64 compbit_base_post_divide64;
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
compbit_store_iova = nvgpu_mem_get_phys_addr(g,
&cbc->compbit_store.mem);
} else
#endif
{
compbit_store_iova = nvgpu_mem_get_addr(g,
&cbc->compbit_store.mem);
}
/* must be aligned to 64 KB */
compbit_store_iova = round_up(compbit_store_iova, (u64)SZ_64K);
compbit_base_post_divide64 = compbit_store_iova >>
fb_mmu_cbc_base_address_alignment_shift_v();
do_div(compbit_base_post_divide64, nvgpu_ltc_get_ltc_count(g));
compbit_base_post_divide = u64_lo32(compbit_base_post_divide64);
compbit_base_post_multiply64 = ((u64)compbit_base_post_divide *
nvgpu_ltc_get_ltc_count(g)) <<
fb_mmu_cbc_base_address_alignment_shift_v();
if (compbit_base_post_multiply64 < compbit_store_iova) {
compbit_base_post_divide++;
}
if (g->ops.cbc.fix_config != NULL) {
compbit_base_post_divide =
g->ops.cbc.fix_config(g, (int)compbit_base_post_divide);
}
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(compbit_base_post_divide));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
(u32)(compbit_store_iova >> 32),
(u32)(compbit_store_iova & U32_MAX),
compbit_base_post_divide);
nvgpu_log(g, gpu_dbg_fn, "cbc base %x",
nvgpu_readl(g, fb_mmu_cbc_base_r()));
cbc->compbit_store.base_hw = compbit_base_post_divide;
}
#endif

65
drivers/gpu/nvgpu/hal/fb/fb_tu104.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -100,69 +100,6 @@ int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
void tu104_fb_cbc_get_alignment(struct gk20a *g,
u64 *base_divisor, u64 *top_divisor)
{
u64 ltc_count = (u64)nvgpu_ltc_get_ltc_count(g);
if (base_divisor != NULL) {
*base_divisor =
ltc_count << fb_mmu_cbc_base_alignment_shift_v();
}
if (top_divisor != NULL) {
*top_divisor =
ltc_count << fb_mmu_cbc_top_alignment_shift_v();
}
}
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u64 base_divisor;
u64 top_divisor;
u64 compbit_store_base;
u64 compbit_store_pa;
u64 cbc_start_addr, cbc_end_addr;
u64 cbc_top;
u64 cbc_top_size;
u32 cbc_max;
g->ops.fb.cbc_get_alignment(g, &base_divisor, &top_divisor);
compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
compbit_store_base = DIV_ROUND_UP(compbit_store_pa, base_divisor);
cbc_start_addr = compbit_store_base * base_divisor;
cbc_end_addr = cbc_start_addr + cbc->compbit_backing_size;
cbc_top = (cbc_end_addr / top_divisor);
cbc_top_size = u64_lo32(cbc_top) - compbit_store_base;
nvgpu_assert(cbc_top_size < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_top_r(),
fb_mmu_cbc_top_size_f(U32(cbc_top_size)));
cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r());
cbc_max = set_field(cbc_max,
fb_mmu_cbc_max_comptagline_m(),
fb_mmu_cbc_max_comptagline_f(cbc->max_comptag_lines));
nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max);
nvgpu_assert(compbit_store_base < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(U32(compbit_store_base)));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%llx\n",
(u32)(compbit_store_pa >> 32),
(u32)(compbit_store_pa & 0xffffffffU),
compbit_store_base);
cbc->compbit_store.base_hw = compbit_store_base;
}
#endif
static int tu104_fb_wait_mmu_bind(struct gk20a *g)
{
struct nvgpu_timeout timeout;

103
drivers/gpu/nvgpu/hal/fb/fb_tu104_fusa.c Normal file
View File

@@ -0,0 +1,103 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/trace.h>
#include <nvgpu/log.h>
#include <nvgpu/types.h>
#include <nvgpu/timers.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/nvgpu_init.h>
#include "hal/fb/fb_gv11b.h"
#include "hal/fb/fb_gv100.h"
#include "hal/mc/mc_tu104.h"
#include "fb_tu104.h"
#include "nvgpu/hw/tu104/hw_fb_tu104.h"
#include "nvgpu/hw/tu104/hw_func_tu104.h"
#ifdef CONFIG_NVGPU_COMPRESSION
void tu104_fb_cbc_get_alignment(struct gk20a *g,
u64 *base_divisor, u64 *top_divisor)
{
u64 ltc_count = (u64)nvgpu_ltc_get_ltc_count(g);
if (base_divisor != NULL) {
*base_divisor =
ltc_count << fb_mmu_cbc_base_alignment_shift_v();
}
if (top_divisor != NULL) {
*top_divisor =
ltc_count << fb_mmu_cbc_top_alignment_shift_v();
}
}
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u64 base_divisor;
u64 top_divisor;
u64 compbit_store_base;
u64 compbit_store_pa;
u64 cbc_start_addr, cbc_end_addr;
u64 cbc_top;
u64 cbc_top_size;
u32 cbc_max;
g->ops.fb.cbc_get_alignment(g, &base_divisor, &top_divisor);
compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
compbit_store_base = DIV_ROUND_UP(compbit_store_pa, base_divisor);
cbc_start_addr = compbit_store_base * base_divisor;
cbc_end_addr = cbc_start_addr + cbc->compbit_backing_size;
cbc_top = (cbc_end_addr / top_divisor);
cbc_top_size = u64_lo32(cbc_top) - compbit_store_base;
nvgpu_assert(cbc_top_size < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_top_r(),
fb_mmu_cbc_top_size_f(U32(cbc_top_size)));
cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r());
cbc_max = set_field(cbc_max,
fb_mmu_cbc_max_comptagline_m(),
fb_mmu_cbc_max_comptagline_f(cbc->max_comptag_lines));
nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max);
nvgpu_assert(compbit_store_base < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(U32(compbit_store_base)));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%llx\n",
(u32)(compbit_store_pa >> 32),
(u32)(compbit_store_pa & 0xffffffffU),
compbit_store_base);
cbc->compbit_store.base_hw = compbit_store_base;
}
#endif

4
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -915,7 +915,9 @@ static const struct gops_fb ga100_ops_fb = {
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gv100_fb_set_mmu_debug_mode,
#endif
#ifdef CONFIG_NVGPU_NON_FUSA
.tlb_invalidate = fb_tu104_tlb_invalidate,
#endif
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
.mmu_invalidate_replay = tu104_fb_mmu_invalidate_replay,
@@ -938,9 +940,11 @@ static const struct gops_fb ga100_ops_fb = {
.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
.get_num_active_ltcs = ga10b_fb_get_num_active_ltcs,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
#ifdef CONFIG_NVGPU_DGPU
.get_vidmem_size = tu104_fb_get_vidmem_size,
#endif
#endif
#ifdef CONFIG_NVGPU_MIG
.config_veid_smc_map = ga10b_fb_config_veid_smc_map,
.set_smc_eng_config = ga10b_fb_set_smc_eng_config,

8
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -802,7 +802,9 @@ static const struct gops_fb tu104_ops_fb = {
.fbpa_ecc_free = tu104_fbpa_ecc_free,
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gp106_fb_init_fs_state,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.set_atomic_mode = tu104_fb_set_atomic_mode,
#endif
.set_mmu_page_size = NULL,
.mmu_ctrl = gm20b_fb_mmu_ctrl,
.mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl,
@@ -825,14 +827,18 @@ static const struct gops_fb tu104_ops_fb = {
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gv100_fb_set_mmu_debug_mode,
#endif
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.tlb_invalidate = fb_tu104_tlb_invalidate,
#endif
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
.mmu_invalidate_replay = tu104_fb_mmu_invalidate_replay,
#endif
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.mem_unlock = gv100_fb_memory_unlock,
.init_nvlink = gv100_fb_init_nvlink,
.enable_nvlink = gv100_fb_enable_nvlink,
#endif
.init_fbpa = tu104_fbpa_init,
.handle_fbpa_intr = tu104_fbpa_handle_intr,
.write_mmu_fault_buffer_lo_hi = tu104_fb_write_mmu_fault_buffer_lo_hi,
@@ -849,10 +855,12 @@ static const struct gops_fb tu104_ops_fb = {
.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled,
.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
#ifdef CONFIG_NVGPU_DGPU
.get_vidmem_size = tu104_fb_get_vidmem_size,
#endif
.apply_pdb_cache_errata = tu104_fb_apply_pdb_cache_errata,
#endif
};
static const struct gops_nvdec tu104_ops_nvdec = {

81
drivers/gpu/nvgpu/hal/mm/cache/flush_gk20a.c vendored
View File

@@ -1,81 +0,0 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/trace.h>
#include <nvgpu/mm.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/timers.h>
#include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
#include "flush_gk20a.h"
#ifdef CONFIG_NVGPU_COMPRESSION
void gk20a_mm_cbc_clean(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
u32 data;
struct nvgpu_timeout timeout;
u32 retries = 200;
nvgpu_log_fn(g, " ");
gk20a_busy_noresume(g);
if (nvgpu_is_powered_off(g)) {
goto hw_was_off;
}
if (g->ops.mm.get_flush_retries != NULL) {
retries = g->ops.mm.get_flush_retries(g, NVGPU_FLUSH_CBC_CLEAN);
}
nvgpu_timeout_init_retry(g, &timeout, retries);
nvgpu_mutex_acquire(&mm->l2_op_lock);
/* Flush all dirty lines from the CBC to L2 */
nvgpu_writel(g, flush_l2_clean_comptags_r(),
flush_l2_clean_comptags_pending_busy_f());
do {
data = nvgpu_readl(g, flush_l2_clean_comptags_r());
if (flush_l2_clean_comptags_outstanding_v(data) ==
flush_l2_clean_comptags_outstanding_true_v() ||
flush_l2_clean_comptags_pending_v(data) ==
flush_l2_clean_comptags_pending_busy_v()) {
nvgpu_log_info(g, "l2_clean_comptags 0x%x", data);
nvgpu_udelay(5);
} else {
break;
}
} while (nvgpu_timeout_expired_msg(&timeout,
"l2_clean_comptags too many retries") == 0);
nvgpu_mutex_release(&mm->l2_op_lock);
hw_was_off:
gk20a_idle_nosuspend(g);
}
#endif

51
drivers/gpu/nvgpu/hal/mm/cache/flush_gk20a_fusa.c vendored
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -223,3 +223,52 @@ int gk20a_mm_l2_flush(struct gk20a *g, bool invalidate)
return err;
}
#ifdef CONFIG_NVGPU_COMPRESSION
void gk20a_mm_cbc_clean(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
u32 data;
struct nvgpu_timeout timeout;
u32 retries = 200;
nvgpu_log_fn(g, " ");
gk20a_busy_noresume(g);
if (nvgpu_is_powered_off(g)) {
goto hw_was_off;
}
if (g->ops.mm.get_flush_retries != NULL) {
retries = g->ops.mm.get_flush_retries(g, NVGPU_FLUSH_CBC_CLEAN);
}
nvgpu_timeout_init_retry(g, &timeout, retries);
nvgpu_mutex_acquire(&mm->l2_op_lock);
/* Flush all dirty lines from the CBC to L2 */
nvgpu_writel(g, flush_l2_clean_comptags_r(),
flush_l2_clean_comptags_pending_busy_f());
do {
data = nvgpu_readl(g, flush_l2_clean_comptags_r());
if (flush_l2_clean_comptags_outstanding_v(data) ==
flush_l2_clean_comptags_outstanding_true_v() ||
flush_l2_clean_comptags_pending_v(data) ==
flush_l2_clean_comptags_pending_busy_v()) {
nvgpu_log_info(g, "l2_clean_comptags 0x%x", data);
nvgpu_udelay(5);
} else {
break;
}
} while (nvgpu_timeout_expired_msg(&timeout,
"l2_clean_comptags too many retries") == 0);
nvgpu_mutex_release(&mm->l2_op_lock);
hw_was_off:
gk20a_idle_nosuspend(g);
}
#endif

2
drivers/gpu/nvgpu/include/nvgpu/posix/utils.h
View File

@@ -216,7 +216,6 @@
*/
#define round_mask(x, y) ((__typeof__(x))((y) - 1U))
#ifdef CONFIG_NVGPU_NON_FUSA
/**
* @brief Round up the value of its argument \a x.
*
@@ -230,7 +229,6 @@
* @return Rounded up value of \a x.
*/
#define round_up(x, y) ((((x) - 1U) | round_mask(x, y)) + 1U)
#endif
/**
* @brief Round down the value of its argument \a x.

35
drivers/gpu/nvgpu/os/posix/contig_pool.c Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/nvgpu_ivm.h>
#include <nvgpu/gk20a.h>
int nvgpu_cbc_contig_init(struct gk20a *g)
{
(void)g;
return 0;
}
void nvgpu_cbc_contig_deinit(struct gk20a *g)
{
(void)g;
}

14
drivers/gpu/nvgpu/os/posix/posix-comptags.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,11 +28,16 @@
void gk20a_get_comptags(struct nvgpu_os_buffer *buf,
struct gk20a_comptags *comptags)
{
(void)buf;
(void)comptags;
}
int gk20a_alloc_comptags(struct gk20a *g, struct nvgpu_os_buffer *buf,
struct gk20a_comptag_allocator *allocator)
{
(void)g;
(void)buf;
(void)allocator;
return -ENODEV;
}
@@ -41,14 +46,21 @@ void gk20a_alloc_or_get_comptags(struct gk20a *g,
struct gk20a_comptag_allocator *allocator,
struct gk20a_comptags *comptags)
{
(void)g;
(void)buf;
(void)allocator;
(void)comptags;
}
bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf)
{
(void)buf;
return false;
}
void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf,
bool clear_successful)
{
(void)buf;
(void)clear_successful;
}

1
libs/igpu/libnvgpu-drv-igpu_safe.export
View File

@@ -81,6 +81,7 @@ gm20b_gr_falcon_submit_fecs_method_op
gm20b_gr_falcon_ctrl_ctxsw
gm20b_bus_bar1_bind
gp10b_bus_bar2_bind
gp10b_fb_compression_page_size
gp10b_get_max_page_table_levels
gp10b_mm_get_default_va_sizes
gp10b_mm_get_iommu_bit