From 3591704fa35f2d56f3e5e09e02acb69f2f46cbb6 Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Wed, 8 May 2019 16:22:08 +0530 Subject: [PATCH] gpu: nvgpu: obj_ctx: fix unsigned int cast cert error Fix CERT-C error for translating size from "unsigned long" to "unsigned int". Error: CERT INT31-C: nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:300: cert_violation: Casting "size" from "unsigned long" to "unsigned int" without checking its value may result in lost or misinterpreted data. JIRA NVGPU-3409 Change-Id: I304fe39049d4f15361b23970ca2bcaecd2050ca3 Signed-off-by: Nitin Kumbhar Reviewed-on: https://git-master.nvidia.com/r/2114536 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 4 ++-- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 4 ++-- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c | 4 ++-- drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index 850b02f8e..2da88ed7f 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -284,7 +284,7 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_config *config, struct nvgpu_gr_ctx *gr_ctx, bool patch) { u64 addr; - u32 size; + size_t size; nvgpu_log_fn(g, " "); @@ -298,7 +298,7 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g, /* global pagepool buffer */ addr = nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_PAGEPOOL_VA); - size = (u32)nvgpu_gr_global_ctx_get_size(global_ctx_buffer, + size = nvgpu_gr_global_ctx_get_size(global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL); g->ops.gr.init.commit_global_pagepool(g, gr_ctx, addr, size, patch, diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index f486df0fe..54b377b23 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -912,7 +912,7 @@ u32 gm20b_gr_init_pagepool_default_size(struct gk20a *g) } void gm20b_gr_init_commit_global_pagepool(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch, + struct nvgpu_gr_ctx *gr_ctx, u64 addr, size_t size, bool patch, bool global_ctx) { addr = (u64_lo32(addr) >> @@ -929,7 +929,7 @@ void gm20b_gr_init_commit_global_pagepool(struct gk20a *g, } nvgpu_assert(u64_hi32(addr) == 0U); - nvgpu_log_info(g, "pagepool buffer addr : 0x%016llx, size : %d", + nvgpu_log_info(g, "pagepool buffer addr : 0x%016llx, size : %lu", addr, size); nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_base_r(), diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index d9eaaf854..81daf20ea 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -85,7 +85,7 @@ void gm20b_gr_init_commit_global_bundle_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u64 addr, u64 size, bool patch); u32 gm20b_gr_init_pagepool_default_size(struct gk20a *g); void gm20b_gr_init_commit_global_pagepool(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch, + struct nvgpu_gr_ctx *gr_ctx, u64 addr, size_t size, bool patch, bool global_ctx); void gm20b_gr_init_commit_global_attrib_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 tpc_count, u32 max_tpc, u64 addr, diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c index 84ad0b10c..4b0124276 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c @@ -345,7 +345,7 @@ u32 gp10b_gr_init_pagepool_default_size(struct gk20a *g) } void gp10b_gr_init_commit_global_pagepool(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch, + struct nvgpu_gr_ctx *gr_ctx, u64 addr, size_t size, bool patch, bool global_ctx) { addr = (u64_lo32(addr) >> @@ -362,7 +362,7 @@ void gp10b_gr_init_commit_global_pagepool(struct gk20a *g, } nvgpu_assert(u64_hi32(addr) == 0U); - nvgpu_log_info(g, "pagepool buffer addr : 0x%016llx, size : %d", + nvgpu_log_info(g, "pagepool buffer addr : 0x%016llx, size : %lu", addr, size); nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_base_r(), diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h index eed5fcee2..c47fe0d9e 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h @@ -51,7 +51,7 @@ void gp10b_gr_init_commit_global_bundle_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u64 addr, u64 size, bool patch); u32 gp10b_gr_init_pagepool_default_size(struct gk20a *g); void gp10b_gr_init_commit_global_pagepool(struct gk20a *g, - struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch, + struct nvgpu_gr_ctx *gr_ctx, u64 addr, size_t size, bool patch, bool global_ctx); void gp10b_gr_init_commit_global_attrib_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 tpc_count, u32 max_tpc, u64 addr, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 36e2cf094..d70a15129 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -753,7 +753,7 @@ struct gpu_ops { bool patch); u32 (*pagepool_default_size)(struct gk20a *g); void (*commit_global_pagepool)(struct gk20a *g, - struct nvgpu_gr_ctx *ch_ctx, u64 addr, u32 size, + struct nvgpu_gr_ctx *ch_ctx, u64 addr, size_t size, bool patch, bool global_ctx); void (*commit_global_attrib_cb)(struct gk20a *g, struct nvgpu_gr_ctx *ch_ctx, u32 tpc_count,