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gpu: nvgpu: Rework engine management to work with vGPU

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Currently the vGPU engine management rewrites a lot of the common
device agnostic engine management code.

With the new top HAL parsing one device at a time, it is now more
easily possible to tie the vGPU into the new common device framework
by implementing the top HAL but with the vGPU engine list backend.

This lets the vGPU inherit all the common engine and device
management code. By doing so the vGPU HAL need only implement a
trivial and simple HAL.

This also gets us a step closer to merging all of the CE init
code: logically it just iterates through all CE engines whatever
they may be. The only reason this differs between chips is because
of the swap from CE0-2 to LCEs in the Pascal generation. This could
be abstracted by the unit code easily enough.

Also, the pbdma_id for each engine has to be added to the device
struct. Eventually this was going to happen anyway, since the
device struct will soon replace the nvgpu_engine_info struct.
It's a little bit of an abuse but might be worth it long term. If
not, it should not be difficult to replace uses of dev->pbdma_id
with a proper lookup of PBDMA ID based on the device info.

JIRA NVGPU-5421

Change-Id: Ie8dcd3b0150184d58ca0f78940c2e7ca72994e64
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351877
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-06-17 11:43:00 -05:00
parent 42ff9ca4d4
commit 359fc24aaf
23 changed files with 234 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c
View File

@@ -37,7 +37,6 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
enum nvgpu_fifo_engine engine_enum;
u32 i;
u32 gr_runlist_id;
u32 pbdma_mask = 0U;
u32 lce_num_entries = 0;
bool found;
@@ -49,6 +48,7 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
for (i = 0; i < lce_num_entries; i++) {
const struct nvgpu_device *dev;
struct nvgpu_device *dev_rw;
struct nvgpu_engine_info *info;
dev = nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
@@ -56,17 +56,26 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
nvgpu_err(g, "Failed to get LCE device %u", i);
return -EINVAL;
}
found = g->ops.fifo.find_pbdma_for_runlist(g,
dev->runlist_id,
&pbdma_mask);
if (!found) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
dev_rw = (struct nvgpu_device *)dev;
info = &g->fifo.engine_info[dev->engine_id];
/*
* vGPU consideration. Not present in older chips. See
* nvgpu_engine_init_from_device_info() for more details in the
* comments.
*/
if (g->ops.fifo.find_pbdma_for_runlist != NULL) {
found = g->ops.fifo.find_pbdma_for_runlist(g,
dev->runlist_id,
&dev_rw->pbdma_id);
if (!found) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
}
info->pbdma_id = dev->pbdma_id;
engine_enum = nvgpu_engine_enum_from_dev(g, dev);
/* GR and GR_COPY shares same runlist_id */
if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) &&
@@ -79,8 +88,6 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
info->intr_mask |= BIT32(dev->intr_id);
info->reset_mask |= BIT32(dev->reset_id);
info->runlist_id = dev->runlist_id;
info->pbdma_id = nvgpu_safe_sub_u32(
nvgpu_safe_cast_u64_to_u32(nvgpu_ffs(pbdma_mask)), 1U);
info->inst_id = dev->inst_id;
info->pri_base = dev->pri_base;
info->engine_id = dev->engine_id;

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -28,7 +28,6 @@
#include <nvgpu/pm_reservation.h>
#include <nvgpu/runlist.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/engines.h>
#include <nvgpu/perfbuf.h>
#include <nvgpu/cyclestats_snapshot.h>
#include <nvgpu/fifo/userd.h>
@@ -680,7 +679,6 @@ static const struct gpu_ops gm20b_ops = {
},
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gm20b_engine_init_ce_info,
},
.pbdma = {

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -27,7 +27,6 @@
#include <nvgpu/debugger.h>
#include <nvgpu/pm_reservation.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/engines.h>
#include <nvgpu/runlist.h>
#include <nvgpu/fifo/userd.h>
#include <nvgpu/perfbuf.h>
@@ -768,7 +767,6 @@ static const struct gpu_ops gp10b_ops = {
},
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -34,7 +34,6 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/fuse.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/engines.h>
#include <nvgpu/preempt.h>
#include <nvgpu/regops.h>
#include <nvgpu/gr/gr_falcon.h>
@@ -980,7 +979,6 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
},
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -221,7 +221,6 @@
#include <nvgpu/debugger.h>
#include <nvgpu/pm_reservation.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/engines.h>
#include <nvgpu/runlist.h>
#include <nvgpu/fifo/userd.h>
#include <nvgpu/perfbuf.h>
@@ -1012,7 +1011,6 @@ static const struct gpu_ops tu104_ops = {
},
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {

3
drivers/gpu/nvgpu/hal/rc/rc_gk20a.c
View File

@@ -62,8 +62,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 eng_bitmask,
nvgpu_runlist_lock_active_runlists(g);
if (id_is_known) {
engine_ids = nvgpu_engine_get_mask_on_id(g,
hw_id, id_is_tsg);
engine_ids = nvgpu_engine_get_mask_on_id(g, hw_id, id_is_tsg);
ref_id = hw_id;
ref_type = id_is_tsg ?
fifo_engine_status_id_type_tsgid_v() :

2
drivers/gpu/nvgpu/hal/top/top_gm20b_fusa.c
View File

@@ -71,7 +71,7 @@ void gm20b_device_info_parse_enum(struct gk20a *g, u32 table_entry,
}
/*
* Parse the device starting at *i. This will return a valid device struct
* Parse the device starting at *token. This will return a valid device struct
* pointer if a device was detected and parsed, NULL otherwise.
*/
struct nvgpu_device *gm20b_top_parse_next_dev(struct gk20a *g, u32 *token)

6
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
View File

@@ -54,6 +54,7 @@
#include "hal/class/class_gp10b.h"
#include "hal/fifo/fifo_gk20a.h"
#include "hal/fifo/engines_gm20b.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
#include "hal/fifo/ramin_gk20a.h"
@@ -92,10 +93,10 @@
#include "common/vgpu/init/init_vgpu.h"
#include "common/vgpu/fb/fb_vgpu.h"
#include "common/vgpu/top/top_vgpu.h"
#include "common/vgpu/fifo/fifo_vgpu.h"
#include "common/vgpu/fifo/channel_vgpu.h"
#include "common/vgpu/fifo/tsg_vgpu.h"
#include "common/vgpu/fifo/engines_vgpu.h"
#include "common/vgpu/fifo/preempt_vgpu.h"
#include "common/vgpu/fifo/runlist_vgpu.h"
#include "common/vgpu/fifo/ramfc_vgpu.h"
@@ -497,7 +498,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
},
.engine = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.init_info = vgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.setup_sw = NULL,
@@ -852,6 +853,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.get_max_fbps_count = vgpu_gr_get_max_fbps_count,
.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
.parse_next_device = vgpu_top_parse_next_dev,
},
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,

6
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -33,6 +33,7 @@
#include "hal/class/class_gv11b.h"
#include "hal/fifo/fifo_gv11b.h"
#include "hal/fifo/preempt_gv11b.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
@@ -110,10 +111,10 @@
#include "common/vgpu/init/init_vgpu.h"
#include "common/vgpu/fb/fb_vgpu.h"
#include "common/vgpu/top/top_vgpu.h"
#include "common/vgpu/fifo/fifo_vgpu.h"
#include "common/vgpu/fifo/channel_vgpu.h"
#include "common/vgpu/fifo/tsg_vgpu.h"
#include "common/vgpu/fifo/engines_vgpu.h"
#include "common/vgpu/fifo/preempt_vgpu.h"
#include "common/vgpu/fifo/runlist_vgpu.h"
#include "common/vgpu/fifo/ramfc_vgpu.h"
@@ -616,7 +617,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
},
.engine = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.init_info = vgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.setup_sw = NULL,
@@ -977,6 +978,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_max_fbps_count = vgpu_gr_get_max_fbps_count,
.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
.parse_next_device = vgpu_top_parse_next_dev,
},
.chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
.get_litter_value = gv11b_get_litter_value,