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gpu: nvgpu: Rework engine management to work with vGPU

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Currently the vGPU engine management rewrites a lot of the common
device agnostic engine management code.

With the new top HAL parsing one device at a time, it is now more
easily possible to tie the vGPU into the new common device framework
by implementing the top HAL but with the vGPU engine list backend.

This lets the vGPU inherit all the common engine and device
management code. By doing so the vGPU HAL need only implement a
trivial and simple HAL.

This also gets us a step closer to merging all of the CE init
code: logically it just iterates through all CE engines whatever
they may be. The only reason this differs between chips is because
of the swap from CE0-2 to LCEs in the Pascal generation. This could
be abstracted by the unit code easily enough.

Also, the pbdma_id for each engine has to be added to the device
struct. Eventually this was going to happen anyway, since the
device struct will soon replace the nvgpu_engine_info struct.
It's a little bit of an abuse but might be worth it long term. If
not, it should not be difficult to replace uses of dev->pbdma_id
with a proper lookup of PBDMA ID based on the device info.

JIRA NVGPU-5421

Change-Id: Ie8dcd3b0150184d58ca0f78940c2e7ca72994e64
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351877
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-06-17 11:43:00 -05:00
parent 42ff9ca4d4
commit 359fc24aaf
23 changed files with 234 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
userspace/units/fifo/engine/nvgpu-engine.c
View File

@@ -81,20 +81,8 @@ static void subtest_setup(u32 branches)
#define F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM BIT(0)
#define F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM BIT(1)
#define F_ENGINE_SETUP_SW_INIT_INFO_FAIL BIT(2)
#define F_ENGINE_SETUP_SW_LAST BIT(3)
static int stub_engine_init_info_EINVAL(struct nvgpu_fifo *f)
{
return -EINVAL;
}
static int stub_engine_init_info(struct nvgpu_fifo *f)
{
return 0;
}
int test_engine_setup_sw(struct unit_module *m,
struct gk20a *g, void *args)
{
@@ -105,12 +93,10 @@ int test_engine_setup_sw(struct unit_module *m,
int ret = UNIT_FAIL;
int err;
u32 fail = F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM |
F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM |
F_ENGINE_SETUP_SW_INIT_INFO_FAIL;
F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM;
const char *labels[] = {
"engine_info_nomem",
"engine_list_nomem",
"init_info_fail",
};
u32 prune = fail;
@@ -142,10 +128,6 @@ int test_engine_setup_sw(struct unit_module *m,
nvgpu_posix_enable_fault_injection(kmem_fi, true, 1);
}
g->ops.engine.init_info =
branches & F_ENGINE_SETUP_SW_INIT_INFO_FAIL ?
stub_engine_init_info_EINVAL : stub_engine_init_info;
err = nvgpu_engine_setup_sw(g);
if (branches & fail) {

14
userspace/units/fifo/fifo/nvgpu-fifo.c
View File

@@ -228,11 +228,6 @@ static const char *f_fifo_init[] = {
"fifo setup hw fail",
};
static int stub_nvgpu_engine_init_info(struct nvgpu_fifo *f)
{
return 0;
}
static int stub_init_fifo_setup_hw_fail(struct gk20a *g)
{
return -1;
@@ -299,15 +294,6 @@ int test_init_support(struct unit_module *m, struct gk20a *g, void *args)
(branches & F_FIFO_SETUP_SW_PBDMA_NULL) ?
NULL : gops.pbdma.setup_sw;
/*
* Replace engine init_info with stub when
* PBDMA setup_sw is NULL
*/
g->ops.engine.init_info =
(branches & F_FIFO_SETUP_SW_PBDMA_NULL) ?
stub_nvgpu_engine_init_info :
gops.engine.init_info;
g->ops.pbdma.cleanup_sw =
(branches & (F_FIFO_CLEANUP_SW_PBDMA_NULL |
F_FIFO_SETUP_SW_PBDMA_NULL)) ?