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gpu: nvgpu: Add translation for NVGPU MM flags

Browse Source 
Add a translation layer to convert from the NVGPU_AS_* flags to
to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags.
This allows the common MM code to not depend on the UAPI header
defined for Linux.

In addition to this change a couple of other small changes were
made:

1. Deprecate, print a warning, and ignore usage of the
   NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag.
2. Move the t19x IO coherence flag from the t19x UAPI header
   to the regular UAPI header.

JIRA NVGPU-293

Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599802
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2017-11-16 12:56:53 -08:00
committed by mobile promotions
parent b42fb7ba26
commit 35ae4194a0
16 changed files with 103 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/linux/cde.c
View File

@@ -1052,9 +1052,9 @@ __releases(&l->cde_app->mutex)
/* map the destination buffer */
get_dma_buf(compbits_scatter_buf); /* a ref for nvgpu_vm_map_linux */
err = nvgpu_vm_map_linux(cde_ctx->vm, compbits_scatter_buf, 0,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE |
NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL,
NV_KIND_INVALID,
NVGPU_VM_MAP_CACHEABLE |
NVGPU_VM_MAP_DIRECT_KIND_CTRL,
NVGPU_KIND_INVALID,
compbits_kind, /* incompressible kind */
gk20a_mem_flag_none,
map_offset, map_size,
@@ -1284,7 +1284,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
/* map backing store to gpu virtual space */
vaddr = nvgpu_gmmu_map(ch->vm, &gr->compbit_store.mem,
g->gr.compbit_store.mem.size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_read_only,
false,
gr->compbit_store.mem.aperture);

18
drivers/gpu/nvgpu/common/linux/ioctl_as.c
View File

@@ -32,6 +32,18 @@
#include "ioctl_as.h"
#include "os_linux.h"
static u32 gk20a_as_translate_linux_flags(struct gk20a *g, u32 flags)
{
u32 core_flags = 0;
if (flags & NVGPU_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET)
core_flags |= NVGPU_VM_AREA_ALLOC_FIXED_OFFSET;
if (flags & NVGPU_AS_ALLOC_SPACE_FLAGS_SPARSE)
core_flags |= NVGPU_VM_AREA_ALLOC_SPARSE;
return core_flags;
}
static int gk20a_as_ioctl_bind_channel(
struct gk20a_as_share *as_share,
struct nvgpu_as_bind_channel_args *args)
@@ -62,9 +74,13 @@ static int gk20a_as_ioctl_alloc_space(
struct gk20a_as_share *as_share,
struct nvgpu_as_alloc_space_args *args)
{
struct gk20a *g = gk20a_from_vm(as_share->vm);
gk20a_dbg_fn("");
return nvgpu_vm_area_alloc(as_share->vm, args->pages, args->page_size,
&args->o_a.offset, args->flags);
&args->o_a.offset,
gk20a_as_translate_linux_flags(g,
args->flags));
}
static int gk20a_as_ioctl_free_space(

2
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c
View File

@@ -165,7 +165,7 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
p->pgsz_idx = pgsz_idx;
p->iova = 0;
p->kind = kind_v;
p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0;
p->cacheable = (flags & NVGPU_VM_MAP_CACHEABLE) ? 1 : 0;
p->prot = prot;
p->ctag_offset = ctag_offset;
p->clear_ctags = clear_ctags;

2
drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c
View File

@@ -148,7 +148,7 @@ u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
p->pgsz_idx = pgsz_idx;
p->iova = mapping ? 1 : 0;
p->kind = kind_v;
p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0;
p->cacheable = (flags & NVGPU_VM_MAP_CACHEABLE) ? 1 : 0;
p->prot = prot;
p->ctag_offset = ctag_offset;
p->clear_ctags = clear_ctags;

44
drivers/gpu/nvgpu/common/linux/vm.c
View File

@@ -37,6 +37,30 @@
#include "os_linux.h"
#include "dmabuf.h"
static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
{
u32 core_flags = 0;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET)
core_flags |= NVGPU_VM_MAP_FIXED_OFFSET;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE)
core_flags |= NVGPU_VM_MAP_CACHEABLE;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT)
core_flags |= NVGPU_VM_MAP_IO_COHERENT;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
core_flags |= NVGPU_VM_MAP_L3_ALLOC;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS)
nvgpu_warn(g, "Ignoring deprecated flag: "
"NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS");
return core_flags;
}
static struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf_reverse(
struct vm_gk20a *vm, struct dma_buf *dmabuf, u32 kind)
{
@@ -102,7 +126,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm,
struct gk20a *g = gk20a_from_vm(vm);
struct nvgpu_mapped_buf *mapped_buffer = NULL;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) {
if (flags & NVGPU_VM_MAP_FIXED_OFFSET) {
mapped_buffer = __nvgpu_vm_find_mapped_buf(vm, map_addr);
if (!mapped_buffer)
return NULL;
@@ -167,7 +191,7 @@ int nvgpu_vm_map_linux(struct vm_gk20a *vm,
u64 map_addr = 0ULL;
int err = 0;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET)
if (flags & NVGPU_VM_MAP_FIXED_OFFSET)
map_addr = offset_align;
sgt = gk20a_mm_pin(dev, dmabuf);
@@ -229,15 +253,16 @@ int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
u64 mapping_size,
struct vm_gk20a_mapping_batch *batch)
{
int err = 0;
struct gk20a *g = gk20a_from_vm(vm);
struct dma_buf *dmabuf;
u64 ret_va;
int err = 0;
/* get ref to the mem handle (released on unmap_locked) */
dmabuf = dma_buf_get(dmabuf_fd);
if (IS_ERR(dmabuf)) {
nvgpu_warn(gk20a_from_vm(vm), "%s: fd %d is not a dmabuf",
__func__, dmabuf_fd);
nvgpu_warn(g, "%s: fd %d is not a dmabuf",
__func__, dmabuf_fd);
return PTR_ERR(dmabuf);
}
@@ -250,9 +275,9 @@ int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
*/
if ((mapping_size > dmabuf->size) ||
(buffer_offset > (dmabuf->size - mapping_size))) {
nvgpu_err(gk20a_from_vm(vm),
"buf size %llx < (offset(%llx) + map_size(%llx))\n",
(u64)dmabuf->size, buffer_offset, mapping_size);
nvgpu_err(g,
"buf size %llx < (offset(%llx) + map_size(%llx))\n",
(u64)dmabuf->size, buffer_offset, mapping_size);
return -EINVAL;
}
@@ -263,7 +288,8 @@ int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
}
err = nvgpu_vm_map_linux(vm, dmabuf, *offset_align,
flags, compr_kind, incompr_kind,
nvgpu_vm_translate_linux_flags(g, flags),
compr_kind, incompr_kind,
gk20a_mem_flag_none,
buffer_offset,
mapping_size,

8
drivers/gpu/nvgpu/common/mm/gmmu.c
View File

@@ -20,8 +20,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <uapi/linux/nvgpu.h>
#include <nvgpu/log.h>
#include <nvgpu/list.h>
#include <nvgpu/dma.h>
@@ -682,12 +680,12 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
.pgsz = pgsz_idx,
.kind_v = kind_v,
.ctag = (u64)ctag_offset * (u64)ctag_granularity,
.cacheable = flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
.cacheable = flags & NVGPU_VM_MAP_CACHEABLE,
.rw_flag = rw_flag,
.sparse = sparse,
.priv = priv,
.coherent = flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT,
.valid = !(flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE),
.coherent = flags & NVGPU_VM_MAP_IO_COHERENT,
.valid = !(flags & NVGPU_VM_MAP_UNMAPPED_PTE),
.aperture = aperture
};

6
drivers/gpu/nvgpu/common/mm/gmmu_t19x.c
View File

@@ -20,12 +20,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <uapi/linux/nvgpu.h>
#include <nvgpu/gmmu.h>
#include <nvgpu/vm.h>
void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags)
{
attrs->t19x_attrs.l3_alloc = (bool)(flags &
NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC);
attrs->t19x_attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC);
}

27
drivers/gpu/nvgpu/common/mm/vm.c
View File

@@ -21,8 +21,6 @@
*/
#include <nvgpu/bug.h>
#include <uapi/linux/nvgpu.h>
#include <nvgpu/log.h>
#include <nvgpu/dma.h>
#include <nvgpu/vm.h>
@@ -765,7 +763,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
u8 pte_kind;
if (vm->userspace_managed &&
!(flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET)) {
!(flags & NVGPU_VM_MAP_FIXED_OFFSET)) {
nvgpu_err(g,
"non-fixed-offset mapping not available on "
"userspace managed address spaces");
@@ -774,11 +772,12 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
binfo.flags = flags;
binfo.size = nvgpu_os_buf_get_size(os_buf);
binfo.compr_kind = (vm->enable_ctag && compr_kind != NV_KIND_INVALID ?
compr_kind : NV_KIND_INVALID);
binfo.compr_kind =
(vm->enable_ctag && compr_kind != NVGPU_KIND_INVALID ?
compr_kind : NVGPU_KIND_INVALID);
binfo.incompr_kind = incompr_kind;
if (compr_kind != NV_KIND_INVALID)
if (compr_kind != NVGPU_KIND_INVALID)
map_key_kind = compr_kind;
else
map_key_kind = incompr_kind;
@@ -830,7 +829,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
/*
* Check if we should use a fixed offset for mapping this buffer.
*/
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) {
if (flags & NVGPU_VM_MAP_FIXED_OFFSET) {
err = nvgpu_vm_area_validate_buffer(vm,
map_addr,
map_size,
@@ -848,7 +847,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
goto clean_up;
}
if (binfo.compr_kind != NV_KIND_INVALID) {
if (binfo.compr_kind != NVGPU_KIND_INVALID) {
struct gk20a_comptags comptags = { 0 };
/*
@@ -903,14 +902,14 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
/*
* Figure out the kind and ctag offset for the GMMU page tables
*/
if (binfo.compr_kind != NV_KIND_INVALID && ctag_offset) {
if (binfo.compr_kind != NVGPU_KIND_INVALID && ctag_offset) {
/*
* Adjust the ctag_offset as per the buffer map offset
*/
ctag_offset += phys_offset >>
ilog2(g->ops.fb.compression_page_size(g));
pte_kind = binfo.compr_kind;
} else if (binfo.incompr_kind != NV_KIND_INVALID) {
} else if (binfo.incompr_kind != NVGPU_KIND_INVALID) {
/*
* Incompressible kind, ctag offset will not be programmed
*/
@@ -1093,7 +1092,7 @@ void nvgpu_vm_unmap(struct vm_gk20a *vm, u64 offset,
if (!mapped_buffer)
goto done;
if (mapped_buffer->flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) {
if (mapped_buffer->flags & NVGPU_VM_MAP_FIXED_OFFSET) {
if (nvgpu_vm_unmap_sync_buffer(vm, mapped_buffer))
/*
* Looks like we have failed... Better not continue in
@@ -1118,7 +1117,7 @@ done:
static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
struct nvgpu_ctag_buffer_info *binfo)
{
bool kind_compressible = (binfo->compr_kind != NV_KIND_INVALID);
bool kind_compressible = (binfo->compr_kind != NVGPU_KIND_INVALID);
struct gk20a *g = gk20a_from_vm(vm);
if (kind_compressible &&
@@ -1127,7 +1126,7 @@ static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
/*
* Let's double check that there is a fallback kind
*/
if (binfo->incompr_kind == NV_KIND_INVALID) {
if (binfo->incompr_kind == NVGPU_KIND_INVALID) {
nvgpu_err(g,
"Unsupported page size for compressible "
"kind, but no fallback kind");
@@ -1136,7 +1135,7 @@ static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
nvgpu_log(g, gpu_dbg_map,
"Unsupported page size for compressible "
"kind, demoting to incompressible");
binfo->compr_kind = NV_KIND_INVALID;
binfo->compr_kind = NVGPU_KIND_INVALID;
kind_compressible = false;
}
}

6
drivers/gpu/nvgpu/common/mm/vm_area.c
View File

@@ -20,8 +20,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <uapi/linux/nvgpu.h>
#include <nvgpu/vm.h>
#include <nvgpu/vm_area.h>
@@ -121,7 +119,7 @@ int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
goto clean_up_err;
vma = vm->vma[pgsz_idx];
if (flags & NVGPU_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET)
if (flags & NVGPU_VM_AREA_ALLOC_FIXED_OFFSET)
vaddr_start = nvgpu_alloc_fixed(vma, *addr,
(u64)pages *
(u64)page_size,
@@ -143,7 +141,7 @@ int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
nvgpu_mutex_acquire(&vm->update_gmmu_lock);
if (flags & NVGPU_AS_ALLOC_SPACE_FLAGS_SPARSE) {
if (flags & NVGPU_VM_AREA_ALLOC_SPARSE) {
u64 map_addr = g->ops.mm.gmmu_map(vm, vaddr_start,
NULL,
0,

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1728,7 +1728,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
pm_ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm,
&pm_ctx->mem,
pm_ctx->mem.size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none, true,
pm_ctx->mem.aperture);
if (!pm_ctx->mem.gpu_va) {
@@ -2623,7 +2623,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
}
gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none, true, mem->aperture);
if (!gpu_va)
goto clean_up;
@@ -2641,7 +2641,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
}
gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none, false, mem->aperture);
if (!gpu_va)
goto clean_up;
@@ -2659,7 +2659,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
}
gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none, true, mem->aperture);
if (!gpu_va)
goto clean_up;

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -914,7 +914,7 @@ int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
mem->gpu_va = nvgpu_gmmu_map(vm,
mem,
mem->aligned_size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none,
false,
mem->aperture);

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1350,7 +1350,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
mem->gpu_va = nvgpu_gmmu_map(vm,
mem,
size,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_none,
false,
mem->aperture);

12
drivers/gpu/nvgpu/include/nvgpu/vm.h
View File

@@ -199,6 +199,18 @@ struct vm_gk20a {
u64 syncpt_ro_map_gpu_va;
};
/*
* Mapping flags.
*/
#define NVGPU_VM_MAP_FIXED_OFFSET (1 << 0)
#define NVGPU_VM_MAP_CACHEABLE (1 << 1)
#define NVGPU_VM_MAP_IO_COHERENT (1 << 2)
#define NVGPU_VM_MAP_UNMAPPED_PTE (1 << 3)
#define NVGPU_VM_MAP_DIRECT_KIND_CTRL (1 << 4)
#define NVGPU_VM_MAP_L3_ALLOC (1 << 5)
#define NVGPU_KIND_INVALID -1
void nvgpu_vm_get(struct vm_gk20a *vm);
void nvgpu_vm_put(struct vm_gk20a *vm);

6
drivers/gpu/nvgpu/include/nvgpu/vm_area.h
View File

@@ -57,6 +57,12 @@ nvgpu_vm_area_from_vm_area_list(struct nvgpu_list_node *node)
vm_area_list));
};
/*
* Alloc space flags.
*/
#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET (1 << 0)
#define NVGPU_VM_AREA_ALLOC_SPARSE (1 << 1)
int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
u64 *addr, u32 flags);
int nvgpu_vm_area_free(struct vm_gk20a *vm, u64 addr);

6
include/uapi/linux/nvgpu-t19x.h
View File

@@ -29,12 +29,6 @@
#define NVGPU_GPU_IMPL_GV11B 0x0000000B
#define NVGPU_GPU_IMPL_GV100 0x00000000
/*
* this flag is used in struct nvgpu_as_map_buffer_ex_args
* to provide L3 cache allocation hint
*/
#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
/* subcontexts are available */
#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22)

1
include/uapi/linux/nvgpu.h
View File

@@ -1762,6 +1762,7 @@ struct nvgpu_as_bind_channel_args {
#define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT (1 << 4)
#define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5)
#define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6)
#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
#define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8)
/*