From 362f9a7371496b8f7c39c38e73e77e448c8960b1 Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Mon, 1 Oct 2018 17:27:14 +0530
Subject: [PATCH] gpu: nvgpu: use MC hals to get MC reset mask in perf unit

In common/perf/perf_*.c we right now include MC h/w headers to get
MC reset mask for perfmon

Use MC HAL gops.mc.reset_mask() to get reset mask instead of using
direct MC register headers

Jira NVGPU-1102

Change-Id: I06f0b3638775c07c9e4e7ac80efd479871322d50
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1852620
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/common/perf/perf_gm20b.c | 4 ++--
 drivers/gpu/nvgpu/common/perf/perf_gv11b.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/nvgpu/common/perf/perf_gm20b.c b/drivers/gpu/nvgpu/common/perf/perf_gm20b.c
index 9f1108386..27ca3a3f0 100644
--- a/drivers/gpu/nvgpu/common/perf/perf_gm20b.c
+++ b/drivers/gpu/nvgpu/common/perf/perf_gm20b.c
@@ -23,13 +23,13 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/unit.h>
 
 #include "perf_gm20b.h"
 
 #include "gk20a/gk20a.h"
 
 #include <nvgpu/hw/gm20b/hw_perf_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
 
 bool gm20b_perf_get_membuf_overflow_status(struct gk20a *g)
 {
@@ -55,7 +55,7 @@ void gm20b_perf_membuf_reset_streaming(struct gk20a *g)
 	u32 engine_status;
 	u32 num_unread_bytes;
 
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	engine_status = nvgpu_readl(g, perf_pmasys_enginestatus_r());
 	WARN_ON(0U ==
diff --git a/drivers/gpu/nvgpu/common/perf/perf_gv11b.c b/drivers/gpu/nvgpu/common/perf/perf_gv11b.c
index 2ba756080..d7a0565db 100644
--- a/drivers/gpu/nvgpu/common/perf/perf_gv11b.c
+++ b/drivers/gpu/nvgpu/common/perf/perf_gv11b.c
@@ -23,13 +23,13 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/unit.h>
 
 #include "perf_gv11b.h"
 
 #include "gk20a/gk20a.h"
 
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 
 bool gv11b_perf_get_membuf_overflow_status(struct gk20a *g)
 {
@@ -55,7 +55,7 @@ void gv11b_perf_membuf_reset_streaming(struct gk20a *g)
 	u32 engine_status;
 	u32 num_unread_bytes;
 
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	engine_status = nvgpu_readl(g, perf_pmasys_enginestatus_r());
 	WARN_ON(0U ==