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gpu: nvgpu: Add struct gk20a ptr to FUSE APIs

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Add a pointer to struct gk20a to the FUSE APIs. This helps
QNX builds avoid any static data definitions.

Also this change plumbs struct gk20a in some of the Linux clk
code and fixes a few minor style nits.

Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Alex Waterman
2017-08-11 13:35:24 -07:00
committed by mobile promotions
parent 4412728b96
commit 36f02cf497
7 changed files with 44 additions and 43 deletions
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14
drivers/gpu/nvgpu/common/linux/fuse.c
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@@ -15,7 +15,7 @@
#include <nvgpu/fuse.h>
int nvgpu_tegra_get_gpu_speedo_id(void)
int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
{
return tegra_sku_info.gpu_speedo_id;
}
@@ -24,32 +24,32 @@ int nvgpu_tegra_get_gpu_speedo_id(void)
* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
*/
void nvgpu_tegra_fuse_write_bypass(u32 val)
void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
{
tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
}
void nvgpu_tegra_fuse_write_access_sw(u32 val)
void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
{
tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
}
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val)
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
{
tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
}
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val)
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
{
tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
}
int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val)
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
}
int nvgpu_tegra_fuse_read_reserved_calib(u32 *val)
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
{
return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
}