From 3761c468adbbbd4d0339c4bc78acb1f79b90e7cc Mon Sep 17 00:00:00 2001 From: Austin Tajiri Date: Sat, 17 Sep 2022 06:56:29 +0000 Subject: [PATCH] gpu: nvgpu: add channel.get_vmid gops Add a channel.get_vmid gops so that we can pass the proper VMID to gr.fecs_trace.bind_channel in virtualized environments. Jira GVSCI-14708 Change-Id: Ifc4e6aafa33fa7274bdeb000e8c0fd1a7fc849c7 Signed-off-by: Austin Tajiri Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2780108 Reviewed-by: Sagar Kamble Reviewed-by: Vijayakumar Subbu Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/gr/gr_setup.c | 11 ++++++++++- drivers/gpu/nvgpu/include/nvgpu/gops/channel.h | 3 ++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index 470b6933f..f836e70d3 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -242,12 +242,21 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, #ifdef CONFIG_NVGPU_FECS_TRACE if (g->ops.gr.fecs_trace.bind_channel && !c->vpr) { + u32 vmid = 0U; + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) { gr_subctx = nvgpu_tsg_subctx_get_gr_subctx(c->subctx); } + if (g->ops.channel.get_vmid != NULL) { + err = g->ops.channel.get_vmid(c, &vmid); + if (err != 0) { + nvgpu_warn(g, "failed to get vmid from channel. chid=%u", c->chid); + } + } + err = g->ops.gr.fecs_trace.bind_channel(g, &c->inst_block, - gr_subctx, gr_ctx, mappings, tsg->tgid, 0); + gr_subctx, gr_ctx, mappings, tsg->tgid, vmid); if (err != 0) { nvgpu_warn(g, "fail to bind channel for ctxsw trace"); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h index 0b17175c2..07010879b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -142,6 +142,7 @@ struct gops_channel { void (*reset_faulted)(struct gk20a *g, struct nvgpu_channel *ch, bool eng, bool pbdma); void (*clear)(struct nvgpu_channel *ch); + int (*get_vmid)(struct nvgpu_channel *ch, u32 *vmid); #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT int (*set_syncpt)(struct nvgpu_channel *ch);