nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Move PRAMIN functions to nvgpu_mem

Browse Source 
PRAMIN batch access functions are only used by nvgpu_mem. The way
the functions are written is Linux specific, so move the
implementation from common PRAMIN code.

JIRA NVGPU-259

Change-Id: I6e2aba08c98568c651a86fe8ca7f9f5220d67348
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569697
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-09-27 15:13:45 -07:00
committed by mobile promotions
parent 3c37701377
commit 37ec670601
3 changed files with 49 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/gpu/nvgpu/common/linux/nvgpu_mem.c
View File

@@ -102,6 +102,23 @@ void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem)
mem->cpu_va = NULL;
}
static void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, *dest_u32 = *arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
*dest_u32++ = gk20a_readl(g, r);
r += sizeof(u32);
}
*arg = dest_u32;
}
u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
{
u32 data = 0;
@@ -162,6 +179,23 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
}
}
static void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, *src_u32 = *arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
writel_relaxed(*src_u32++, g->regs + r);
r += sizeof(u32);
}
*arg = src_u32;
}
void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
{
if (mem->aperture == APERTURE_SYSMEM && !g->mm.force_pramin) {
@@ -219,6 +253,21 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
}
}
static void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, repeat = **arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
writel_relaxed(repeat, g->regs + r);
r += sizeof(u32);
}
}
void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
u32 c, u32 size)
{

49
drivers/gpu/nvgpu/common/pramin.c
View File

@@ -34,55 +34,6 @@
*/
#define GK20A_FORCE_PRAMIN_DEFAULT false
void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, *dest_u32 = *arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
*dest_u32++ = gk20a_readl(g, r);
r += sizeof(u32);
}
*arg = dest_u32;
}
void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, *src_u32 = *arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
writel_relaxed(*src_u32++, g->regs + r);
r += sizeof(u32);
}
*arg = src_u32;
}
void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg)
{
u32 r = start, repeat = **arg;
if (!g->regs) {
__gk20a_warn_on_no_regs();
return;
}
while (words--) {
writel_relaxed(repeat, g->regs + r);
r += sizeof(u32);
}
}
/*
* The PRAMIN range is 1 MB, must change base addr if a buffer crosses that.
* This same loop is used for read/write/memset. Offset and size in bytes.

7
drivers/gpu/nvgpu/include/nvgpu/pramin.h
View File

@@ -36,13 +36,6 @@ struct nvgpu_mem;
typedef void (*pramin_access_batch_fn)(struct gk20a *g, u32 start, u32 words,
u32 **arg);
/*
* Generally useful batch functions.
*/
void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg);
void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg);
void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg);
void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
u32 offset, u32 size,
pramin_access_batch_fn loop, u32 **arg);