From 3856381b43fae6e031d6f9871ee6c5fb3feab27c Mon Sep 17 00:00:00 2001 From: tkudav Date: Tue, 24 Mar 2020 17:38:48 +0530 Subject: [PATCH] gpu: nvgpu: Clear nvlink error persistent state Error logging bits within the nvlink blocks like TLC and MIF are persistent through reset, to enable them to be polled following a reset event. That means that they are in an unknown state at cold reset, and may contain error state after a warm reset event. Software is expected to reset them, either by writing ones to the status bits or by writing to the DEBUG_RESET register at the IOCTRL top level, to clear the state out before enabling error reporting. JIRA NVGPU-4352 Change-Id: Iab4e96388fd827c0d694eada61b20f24bbddd1ff Signed-off-by: tkudav Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317683 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c index 393c165a9..1688dffe1 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c @@ -162,13 +162,16 @@ static int gv100_nvlink_enable_links_pre_top(struct gk20a *g, IOCTRL_REG_WR32(g, ioctrl_reset_r(), reg); nvgpu_udelay(delay); + /* Clear warm reset persistent state */ reg = IOCTRL_REG_RD32(g, ioctrl_debug_reset_r()); - reg &= ~ioctrl_debug_reset_link_f(BIT32(link_id)); + reg &= ~(ioctrl_debug_reset_link_f(1U) | + ioctrl_debug_reset_common_f(1U)); IOCTRL_REG_WR32(g, ioctrl_debug_reset_r(), reg); nvgpu_udelay(delay); - reg |= ioctrl_debug_reset_link_f(BIT32(link_id)); + reg |= (ioctrl_debug_reset_link_f(1U) | + ioctrl_debug_reset_common_f(1U)); IOCTRL_REG_WR32(g, ioctrl_debug_reset_r(), reg); nvgpu_udelay(delay);