diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 20d946ffd..9ade1a38e 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -28,14 +28,16 @@ bios: common/vbios/bios_sw_tu104.h, common/vbios/nvlink_bios.c, include/nvgpu/bios.h, - include/nvgpu/nvlink_bios.h] + include/nvgpu/nvlink_bios.h, + include/nvgpu/gops/bios.h, + include/nvgpu/gops/xve.h ] ce: safe: yes owner: Thomas F sources: [ common/ce/ce.c, include/nvgpu/ce.h, - include/nvgpu/gops_ce.h ] + include/nvgpu/gops/ce.h ] deps: ce_app: @@ -56,7 +58,8 @@ debugger: safe: no owner: Deepak N sources: [ common/debugger.c, - include/nvgpu/debugger.h ] + include/nvgpu/debugger.h, + include/nvgpu/gops/debugger.h ] deps: profiler: @@ -65,7 +68,8 @@ profiler: sources: [ common/profiler/profiler.c, include/nvgpu/profiler.h, common/profiler/pm_reservation.c, - include/nvgpu/pm_reservation.h ] + include/nvgpu/pm_reservation.h, + include/nvgpu/gops/profiler.h ] defaults: safe: yes @@ -76,7 +80,7 @@ ecc: owner: Antony C sources: [ common/ecc.c, include/nvgpu/ecc.h, - include/nvgpu/gops_ecc.h ] + include/nvgpu/gops/ecc.h ] deps: log: @@ -103,21 +107,23 @@ fence: io: safe: yes owner: Vinod G - sources: [ common/io/io.c ] + sources: [ common/io/io.c, + include/nvgpu/gops/func.h ] deps: ltc: safe: yes owner: Seshendra G sources: [ common/ltc/ltc.c, - include/nvgpu/gops_ltc.h, + include/nvgpu/gops/ltc.h, include/nvgpu/ltc.h ] cbc: safe: no owner: Seshendra G sources: [ common/cbc/cbc.c, - include/nvgpu/cbc.h ] + include/nvgpu/cbc.h, + include/nvgpu/gops/cbc.h ] regops: safe: no @@ -130,12 +136,12 @@ mc: owner: Seema K sources: [ common/mc/mc.c, include/nvgpu/mc.h, - include/nvgpu/gops_mc.h ] + include/nvgpu/gops/mc.h ] class: safe: yes owner: Seshendra G sources: [ include/nvgpu/class.h, - include/nvgpu/gops_class.h ] + include/nvgpu/gops/class.h ] netlist: safe: yes @@ -158,6 +164,7 @@ nvlink: common/nvlink/init/device_reginit_gv100.c, common/nvlink/init/device_reginit_gv100.h, include/nvgpu/nvlink.h, + include/nvgpu/gops/nvlink.h, include/nvgpu/nvlink_device_reginit.h, include/nvgpu/nvlink_link_mode_transitions.h, include/nvgpu/nvlink_minion.h, @@ -173,7 +180,8 @@ pramin: gpu: dgpu owner: Terje B sources: [ common/pramin.c, - include/nvgpu/pramin.h ] + include/nvgpu/pramin.h, + include/nvgpu/gops/pramin.h ] deps: device: @@ -187,7 +195,7 @@ ptimer: owner: Terje B sources: [ common/ptimer/ptimer.c, include/nvgpu/ptimer.h, - include/nvgpu/gops_ptimer.h ] + include/nvgpu/gops/ptimer.h ] deps: sched: @@ -256,6 +264,7 @@ acr_fusa: common/acr/acr_sw_gv11b.c, common/acr/acr_sw_gv11b.h, common/acr/nvgpu_acr_interface.h, + include/nvgpu/gops/acr.h, include/nvgpu/acr.h ] acr: @@ -276,7 +285,8 @@ sbr: gpu: dgpu sources: [ common/sbr/sbr.c, common/sbr/sbr.h, - include/nvgpu/sbr.h ] + include/nvgpu/sbr.h, + include/nvgpu/gops/sbr.h ] engine_queues: owner: Sagar K @@ -322,7 +332,7 @@ falcon_fusa: sources: [ common/falcon/falcon.c, common/falcon/falcon_sw_gk20a.c, common/falcon/falcon_sw_gk20a.h, - include/nvgpu/gops_falcon.h, + include/nvgpu/gops/falcon.h, include/nvgpu/falcon.h, include/nvgpu/flcnif_cmn.h ] deps: [ ] @@ -333,7 +343,9 @@ falcon: safe: no gpu: dgpu sources: [ common/falcon/falcon_sw_tu104.c, - common/falcon/falcon_sw_tu104.h ] + common/falcon/falcon_sw_tu104.h, + include/nvgpu/gops/gsp.h, + include/nvgpu/gops/nvdec.h ] deps: [ ] tags: @@ -357,16 +369,16 @@ fifo: common/fifo/channel_worker.h, include/nvgpu/channel.h, include/nvgpu/watchdog.h, - include/nvgpu/gops_channel.h, - include/nvgpu/gops_ramfc.h, - include/nvgpu/gops_ramin.h, - include/nvgpu/gops_sync.h, + include/nvgpu/gops/channel.h, + include/nvgpu/gops/ramfc.h, + include/nvgpu/gops/ramin.h, + include/nvgpu/gops/sync.h, include/nvgpu/error_notifier.h ] deps: [ ] tsg: safe: yes sources: [ common/fifo/tsg.c, - include/nvgpu/gops_tsg.h, + include/nvgpu/gops/tsg.h, include/nvgpu/tsg.h ] deps: [ ] submit: @@ -380,19 +392,19 @@ fifo: runlist: safe: yes sources: [ common/fifo/runlist.c, - include/nvgpu/gops_runlist.h, + include/nvgpu/gops/runlist.h, include/nvgpu/runlist.h ] deps: [ ] userd: safe: no sources: [ common/fifo/userd.c, - include/nvgpu/gops_userd.h, + include/nvgpu/gops/userd.h, include/nvgpu/fifo/userd.h ] deps: [ ] pbdma: safe: yes sources: [ common/fifo/pbdma.c, - include/nvgpu/gops_pbdma.h, + include/nvgpu/gops/pbdma.h, include/nvgpu/pbdma.h ] deps: [ ] pbdma_status: @@ -408,7 +420,7 @@ fifo: engines: safe: yes sources: [ common/fifo/engines.c, - include/nvgpu/gops_engine.h, + include/nvgpu/gops/engine.h, include/nvgpu/engines.h ] deps: [] @@ -421,12 +433,12 @@ fifo: fifo: safe: yes sources: [ common/fifo/fifo.c, - include/nvgpu/gops_fifo.h, + include/nvgpu/gops/fifo.h, include/nvgpu/fifo.h ] usermode: safe: yes - sources: [ include/nvgpu/gops_usermode.h ] + sources: [ include/nvgpu/gops/usermode.h ] gr: safe: yes @@ -438,7 +450,7 @@ gr: common/gr/gr_priv.h, common/gr/gr_utils.c, include/nvgpu/gr/gr_utils.h, - include/nvgpu/gops_gr.h, + include/nvgpu/gops/gr.h, include/nvgpu/gr/gr.h ] global_ctx: safe: yes @@ -518,7 +530,8 @@ fbp: owner: Deepak N sources: [ common/fbp/fbp.c, common/fbp/fbp_priv.h, - include/nvgpu/fbp.h ] + include/nvgpu/fbp.h, + include/nvgpu/gops/fbp.h ] init: safe: yes @@ -527,7 +540,8 @@ init: nvgpu: safe: yes sources: [ common/init/nvgpu_init.c, - include/nvgpu/nvgpu_init.h ] + include/nvgpu/nvgpu_init.h, + include/nvgpu/gpu_ops.h ] mm: owner: Alex W @@ -599,7 +613,7 @@ mm: safe: yes sources: [ common/mm/mm.c, include/nvgpu/mm.h, - include/nvgpu/gops_mm.h ] + include/nvgpu/gops/mm.h ] deps: [ ] nvgpu_mem: safe: yes @@ -634,7 +648,7 @@ mm: fuse: safe: yes owner: Seema K - sources: [ include/nvgpu/gops_fuse.h ] + sources: [ include/nvgpu/gops/fuse.h ] perf: safe: no @@ -654,12 +668,14 @@ cyclestats: owner: Deepak N sources: [ common/cyclestats/cyclestats.c, common/cyclestats/cyclestats_priv.h, - include/nvgpu/cyclestats.h ] + include/nvgpu/cyclestats.h, + include/nvgpu/gops/cyclestats.h ] clk_arb: safe: yes gpu: dgpu sources: [ include/nvgpu/clk_arb.h, + include/nvgpu/gops/clk_arb.h, common/clk_arb/clk_arb.c, common/clk_arb/clk_arb_gp10b.c, common/clk_arb/clk_arb_gp10b.h, @@ -671,7 +687,7 @@ therm: owner: Seshendra G sources: [ common/therm/therm.c, include/nvgpu/therm.h, - include/nvgpu/gops_therm.h ] + include/nvgpu/gops/therm.h ] pmu: children: @@ -722,7 +738,7 @@ pmu: safe: yes owner: Mahantesh K sources: [ common/pmu/pmu.c, - include/nvgpu/gops_pmu.h, + include/nvgpu/gops/pmu.h, include/nvgpu/pmu.h ] pmu_rtos_init: @@ -814,6 +830,7 @@ pmu: common/pmu/clk/clk_vin.c, common/pmu/clk/clk_vin.h, common/pmu/clk/clk.h, + include/nvgpu/gops/clk.h, include/nvgpu/pmu/clk/clk.h] ipc: safe: yes @@ -937,7 +954,8 @@ sec2: gpu: dgpu sources: [ common/sec2/sec2.c, include/nvgpu/sec2/sec2.h, - include/nvgpu/sec2/sec2_cmn.h ] + include/nvgpu/sec2/sec2_cmn.h, + include/nvgpu/gops/sec2.h ] ipc: safe: yes owner: Sagar K @@ -1001,12 +1019,17 @@ power_features: safe: yes sources: [ common/power_features/cg/cg.c, include/nvgpu/power_features/cg.h, - include/nvgpu/gops_cg.h ] + include/nvgpu/gops/cg.h ] pg: safe: no sources: [ common/power_features/pg/pg.c, include/nvgpu/power_features/pg.h ] +floorsweep: + owner: Divya S + safe: no + sources: [ include/nvgpu/gops/floorsweep.h ] + swdebug: owner: Alex W safe: no @@ -1020,7 +1043,7 @@ grmgr: sources: [ common/grmgr/grmgr.c, include/nvgpu/grmgr.h, include/nvgpu/mig.h, - include/nvgpu/gops_grmgr.h ] + include/nvgpu/gops/grmgr.h ] ## ## HAL units. Currently they are under common but this needs to change. diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 69d63590e..f1b8b764d 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -6,7 +6,7 @@ bus_fusa: safe: yes owner: Terje B - sources: [ include/nvgpu/gops_bus.h, + sources: [ include/nvgpu/gops/bus.h, hal/bus/bus_gk20a_fusa.c, hal/bus/bus_gk20a.h, hal/bus/bus_gm20b_fusa.c, hal/bus/bus_gm20b.h, @@ -79,7 +79,7 @@ init: priv_ring_fusa: safe: yes owner: Seema K - sources: [ include/nvgpu/gops_priv_ring.h, + sources: [ include/nvgpu/gops/priv_ring.h, hal/priv_ring/priv_ring_gm20b_fusa.c, hal/priv_ring/priv_ring_gm20b.h, hal/priv_ring/priv_ring_gp10b_fusa.c, @@ -635,7 +635,7 @@ mc: fb_fusa: safe: yes owner: Seshendra G - sources: [ include/nvgpu/gops_fb.h, + sources: [ include/nvgpu/gops/fb.h, hal/fb/fb_gm20b_fusa.c, hal/fb/fb_gm20b.h, hal/fb/fb_gv11b_fusa.c, @@ -708,7 +708,7 @@ netlist_fusa: safe: yes owner: Seshendra G gpu: both - sources: [ include/nvgpu/gops_netlist.h, + sources: [ include/nvgpu/gops/netlist.h, hal/netlist/netlist_gv11b_fusa.c, hal/netlist/netlist_gv11b.h ] @@ -778,7 +778,7 @@ func: top_fusa: safe: yes owner: Tejal K - sources: [ include/nvgpu/gops_top.h, + sources: [ include/nvgpu/gops/top.h, hal/top/top_gm20b_fusa.c, hal/top/top_gm20b.h, hal/top/top_gp10b.h, diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c index 2ba7c169d..7de7fd6a6 100644 --- a/drivers/gpu/nvgpu/common/ce/ce.c +++ b/drivers/gpu/nvgpu/common/ce/ce.c @@ -26,7 +26,6 @@ #include #include #include -#include #include int nvgpu_ce_init_support(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/fb/fb.c b/drivers/gpu/nvgpu/common/fb/fb.c index c8ac77fcc..d82568589 100644 --- a/drivers/gpu/nvgpu/common/fb/fb.c +++ b/drivers/gpu/nvgpu/common/fb/fb.c @@ -22,7 +22,6 @@ #include #include -#include #include int nvgpu_init_fb_support(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 45deff8b1..de841f9e8 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 5b1636630..c15c8e096 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -45,7 +45,6 @@ #include #include #include -#include #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT) #include #endif diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 39eeaa182..534d10326 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index 818475833..f6416ee53 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c @@ -35,7 +35,6 @@ #include #include #include -#include int nvgpu_mm_suspend(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c index 3ffec823d..b41151b2c 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c @@ -40,7 +40,6 @@ #include #include #include -#include #include "fb_gv100.h" diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c index edaea4e94..b0586d7a5 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics FIFO (gr host) * - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,7 +28,6 @@ #include #include #include -#include #include "hal/fifo/fifo_gk20a.h" diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c index a835c2075..ac24049e7 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c @@ -30,7 +30,6 @@ #include #include #include -#include #include diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c index 62c5a12c1..8a2447a4e 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c @@ -38,7 +38,6 @@ #ifdef CONFIG_NVGPU_LS_PMU #include #endif -#include #include "preempt_gv11b.h" diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c index ed4111116..908683e20 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c @@ -44,7 +44,6 @@ #include #include #include -#include #include "gr_gk20a.h" #include "gr_pri_gk20a.h" diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c index db99fcc00..ba18d7548 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c @@ -43,7 +43,6 @@ #include #include #include -#include #include "gr_pri_gk20a.h" #include "gr_pri_gv11b.h" diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index 3b4d097a1..7636e602e 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -32,7 +32,6 @@ #include #include #include -#include #include "mc_gm20b.h" diff --git a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c index 3379b1a6d..50aeeaca1 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "hal/mc/mc_gp10b.h" diff --git a/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c index 1d08afa83..575822c42 100644 --- a/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/hal/nvlink/nvlink_gv100.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include "nvlink_gv100.h" diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c index 8485ba24a..82b55dd2a 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c @@ -30,7 +30,6 @@ #include #include #include -#include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/ce.h b/drivers/gpu/nvgpu/include/nvgpu/ce.h index 6348b890e..b6abae23b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ce.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -58,7 +58,7 @@ * External APIs * ------------- * Dynamic interfaces are HAL functions. They are documented here: - * + include/nvgpu/gops_ce.h + * + include/nvgpu/gops/ce.h */ struct gk20a; diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h index 10511ce16..bda5adbe7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h @@ -48,7 +48,7 @@ * The FIFO unit TODO. * * + include/nvgpu/fifo.h - * + include/nvgpu/gops_fifo.h + * + include/nvgpu/gops/fifo.h * * Runlist * ------- @@ -56,7 +56,7 @@ * TODO * * + include/nvgpu/runlist.h - * + include/nvgpu/gops_runlist.h + * + include/nvgpu/gops/runlist.h * * Pbdma * ------- @@ -73,7 +73,7 @@ * * + include/nvgpu/engines.h * + include/nvgpu/engine_status.h - * + include/nvgpu/gops_engine.h + * + include/nvgpu/gops/engine.h * * Preempt * ------- @@ -88,7 +88,7 @@ * TODO * * + include/nvgpu/channel.h - * + include/nvgpu/gops_channel.h + * + include/nvgpu/gops/channel.h * * Tsg * ------- @@ -102,22 +102,22 @@ * * TODO * - * + include/nvgpu/gops_ramin.h - * + include/nvgpu/gops_ramfc.h + * + include/nvgpu/gops/ramin.h + * + include/nvgpu/gops/ramfc.h * * Sync * ---- * * + include/nvgpu/channel_sync.h * + include/nvgpu/channel_sync_syncpt.h - * + include/nvgpu/gops_sync.h + * + include/nvgpu/gops/sync.h * * Usermode * -------- * * TODO * - * + include/nvgpu/gops_usermode.h + * + include/nvgpu/gops/usermode.h * * * Data Structures diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index aa10f79b1..0edd01e81 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -142,36 +142,7 @@ enum nvgpu_profiler_pm_reservation_scope; #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include "hal/clk/clk_gk20a.h" @@ -257,396 +228,6 @@ enum nvgpu_event_id_type { NVGPU_EVENT_ID_MAX = 6, }; -/** - * @addtogroup unit-common-nvgpu - * @{ - */ - -/** - * @brief HAL methods - * - * gpu_ops contains function pointers for the unit HAL interfaces. gpu_ops - * should only contain function pointers! Non-function pointer members should go - * in struct gk20a or be implemented with the boolean flag API defined in - * nvgpu/enabled.h. Each unit should have its own sub-struct in the gpu_ops - * struct. - */ - -struct gpu_ops { - struct { - int (*acr_init)(struct gk20a *g); - int (*acr_construct_execute)(struct gk20a *g); - } acr; - struct { - int (*sbr_pub_load_and_execute)(struct gk20a *g); - } sbr; - - struct { - u32 (*get_full_phys_offset)(struct gk20a *g); - } func; - - struct gops_ecc ecc; - struct gops_ltc ltc; -#ifdef CONFIG_NVGPU_COMPRESSION - struct { - int (*cbc_init_support)(struct gk20a *g); - void (*cbc_remove_support)(struct gk20a *g); - void (*init)(struct gk20a *g, struct nvgpu_cbc *cbc); - u64 (*get_base_divisor)(struct gk20a *g); - int (*alloc_comptags)(struct gk20a *g, - struct nvgpu_cbc *cbc); - int (*ctrl)(struct gk20a *g, enum nvgpu_cbc_op op, - u32 min, u32 max); - u32 (*fix_config)(struct gk20a *g, int base); - } cbc; -#endif - struct gops_ce ce; - struct gops_gr gr; - struct gops_class gpu_class; - struct gops_fb fb; - - struct { - u32 (*falcon_base_addr)(void); - } nvdec; - struct gops_cg cg; - struct gops_fifo fifo; - struct gops_fuse fuse; - struct gops_ramfc ramfc; - struct gops_ramin ramin; - struct gops_runlist runlist; - struct gops_userd userd; - struct gops_engine engine; - struct gops_pbdma pbdma; - struct gops_sync sync; - struct gops_channel channel; - struct gops_tsg tsg; - struct gops_usermode usermode; - struct gops_engine_status engine_status; - struct gops_pbdma_status pbdma_status; - struct gops_netlist netlist; - struct gops_mm mm; - /* - * This function is called to allocate secure memory (memory - * that the CPU cannot see). The function should fill the - * context buffer descriptor (especially fields destroy, sgt, - * size). - */ - int (*secure_alloc)(struct gk20a *g, struct nvgpu_mem *desc_mem, - size_t size, - void (**fn)(struct gk20a *g, struct nvgpu_mem *mem)); - -#ifdef CONFIG_NVGPU_DGPU - struct { - u32 (*data032_r)(u32 i); - } pramin; -#endif - struct gops_therm therm; - struct gops_pmu pmu; - struct { - int (*init_debugfs)(struct gk20a *g); - int (*init_clk_support)(struct gk20a *g); - void (*suspend_clk_support)(struct gk20a *g); - u32 (*get_crystal_clk_hz)(struct gk20a *g); - int (*clk_domain_get_f_points)(struct gk20a *g, - u32 clkapidomain, u32 *pfpointscount, - u16 *pfreqpointsinmhz); - int (*clk_get_round_rate)(struct gk20a *g, u32 api_domain, - unsigned long rate_target, unsigned long *rounded_rate); - int (*get_clk_range)(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); - unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain); - u32 (*get_rate_cntr)(struct gk20a *g, struct namemap_cfg *c); - u32 (*get_cntr_xbarclk_source)(struct gk20a *g); - u32 (*get_cntr_sysclk_source)(struct gk20a *g); - unsigned long (*get_rate)(struct gk20a *g, u32 api_domain); - int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate); - unsigned long (*get_fmax_at_vmin_safe)(struct gk20a *g); - u32 (*get_ref_clock_rate)(struct gk20a *g); - int (*predict_mv_at_hz_cur_tfloor)(struct clk_gk20a *clk, - unsigned long rate); - unsigned long (*get_maxrate)(struct gk20a *g, u32 api_domain); - int (*prepare_enable)(struct clk_gk20a *clk); - void (*disable_unprepare)(struct clk_gk20a *clk); - int (*get_voltage)(struct clk_gk20a *clk, u64 *val); - int (*get_gpcclk_clock_counter)(struct clk_gk20a *clk, u64 *val); - int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val); - int (*get_pll_debug_data)(struct gk20a *g, - struct nvgpu_clk_pll_debug_data *d); - int (*mclk_init)(struct gk20a *g); - void (*mclk_deinit)(struct gk20a *g); - int (*mclk_change)(struct gk20a *g, u16 val); - void (*get_change_seq_time)(struct gk20a *g, s64 *change_time); - void (*change_host_clk_source)(struct gk20a *g); - u32 (*clk_mon_init_domains)(struct gk20a *g); - bool split_rail_support; - bool support_pmgr_domain; - bool support_lpwr_pg; - int (*perf_pmu_vfe_load)(struct gk20a *g); - bool support_vf_point; - u8 lut_num_entries; - } clk; -#ifdef CONFIG_NVGPU_DGPU - struct { - int (*clk_mon_alloc_memory)(struct gk20a *g); - bool (*clk_mon_check_master_fault_status)(struct gk20a *g); - int (*clk_mon_check_status)(struct gk20a *g, - u32 domain_mask); - bool (*clk_mon_check_clk_good)(struct gk20a *g); - bool (*clk_mon_check_pll_lock)(struct gk20a *g); - } clk_mon; -#endif -#ifdef CONFIG_NVGPU_CLK_ARB - struct { - int (*clk_arb_init_arbiter)(struct gk20a *g); - int (*arbiter_clk_init)(struct gk20a *g); - bool (*check_clk_arb_support)(struct gk20a *g); - u32 (*get_arbiter_clk_domains)(struct gk20a *g); - int (*get_arbiter_f_points)(struct gk20a *g, u32 api_domain, - u32 *num_points, u16 *freqs_in_mhz); - int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); - int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain, - u16 *default_mhz); - void (*clk_arb_run_arbiter_cb)(struct nvgpu_clk_arb *arb); - /* This function is inherently unsafe to call while - * arbiter is running arbiter must be blocked - * before calling this function */ - u32 (*get_current_pstate)(struct gk20a *g); - void (*clk_arb_cleanup)(struct nvgpu_clk_arb *arb); - void (*stop_clk_arb_threads)(struct gk20a *g); - } clk_arb; -#endif - struct { - int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); - } pmu_perf; -#ifdef CONFIG_NVGPU_DEBUGGER - struct { - int (*exec_regops)(struct gk20a *g, - struct nvgpu_tsg *tsg, - struct nvgpu_dbg_reg_op *ops, - u32 num_ops, - u32 *flags); - const struct regop_offset_range* ( - *get_global_whitelist_ranges)(void); - u64 (*get_global_whitelist_ranges_count)(void); - const struct regop_offset_range* ( - *get_context_whitelist_ranges)(void); - u64 (*get_context_whitelist_ranges_count)(void); - const u32* (*get_runcontrol_whitelist)(void); - u64 (*get_runcontrol_whitelist_count)(void); - } regops; -#endif - struct gops_mc mc; - - struct { - void (*show_dump)(struct gk20a *g, - struct nvgpu_debug_context *o); - } debug; -#ifdef CONFIG_NVGPU_DEBUGGER - struct { - void (*post_events)(struct nvgpu_channel *ch); - int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, - bool disable_powergate); - } debugger; - struct { - void (*enable_membuf)(struct gk20a *g, u32 size, u64 buf_addr); - void (*disable_membuf)(struct gk20a *g); - void (*init_inst_block)(struct gk20a *g, - struct nvgpu_mem *inst_block); - void (*deinit_inst_block)(struct gk20a *g); - void (*membuf_reset_streaming)(struct gk20a *g); - u32 (*get_membuf_pending_bytes)(struct gk20a *g); - void (*set_membuf_handled_bytes)(struct gk20a *g, - u32 entries, u32 entry_size); - bool (*get_membuf_overflow_status)(struct gk20a *g); - u32 (*get_pmm_per_chiplet_offset)(void); - } perf; - struct { - int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size); - int (*perfbuf_disable)(struct gk20a *g); - int (*init_inst_block)(struct gk20a *g); - void (*deinit_inst_block)(struct gk20a *g); - } perfbuf; -#endif -#ifdef CONFIG_NVGPU_PROFILER - struct { - int (*acquire)(struct gk20a *g, u32 reservation_id, - enum nvgpu_profiler_pm_resource_type pm_resource, - enum nvgpu_profiler_pm_reservation_scope scope, - u32 vmid); - int (*release)(struct gk20a *g, u32 reservation_id, - enum nvgpu_profiler_pm_resource_type pm_resource, - u32 vmid); - void (*release_all_per_vmid)(struct gk20a *g, u32 vmid); - } pm_reservation; -#endif - - u32 (*get_litter_value)(struct gk20a *g, int value); - int (*chip_init_gpu_characteristics)(struct gk20a *g); - - struct gops_bus bus; - - struct gops_ptimer ptimer; - - struct { - int (*bios_sw_init)(struct gk20a *g); - void (*bios_sw_deinit)(struct gk20a *g, - struct nvgpu_bios *bios); - u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i); - bool (*wait_for_bios_init_done)(struct gk20a *g); - } bios; - -#if defined(CONFIG_NVGPU_CYCLESTATS) - struct { - int (*enable_snapshot)(struct nvgpu_channel *ch, - struct gk20a_cs_snapshot_client *client); - void (*disable_snapshot)(struct gk20a *g); - int (*check_data_available)(struct nvgpu_channel *ch, - u32 *pending, - bool *hw_overflow); - void (*set_handled_snapshots)(struct gk20a *g, u32 num); - u32 (*allocate_perfmon_ids)(struct gk20a_cs_snapshot *data, - u32 count); - u32 (*release_perfmon_ids)(struct gk20a_cs_snapshot *data, - u32 start, - u32 count); - int (*detach_snapshot)(struct nvgpu_channel *ch, - struct gk20a_cs_snapshot_client *client); - bool (*get_overflow_status)(struct gk20a *g); - u32 (*get_pending_snapshots)(struct gk20a *g); - u32 (*get_max_buffer_size)(struct gk20a *g); - } css; -#endif -#ifdef CONFIG_NVGPU_DGPU - struct { - int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); - int (*set_speed)(struct gk20a *g, u32 xve_link_speed); - void (*available_speeds)(struct gk20a *g, u32 *speed_mask); - u32 (*xve_readl)(struct gk20a *g, u32 reg); - void (*xve_writel)(struct gk20a *g, u32 reg, u32 val); - void (*disable_aspm)(struct gk20a *g); - void (*reset_gpu)(struct gk20a *g); -#if defined(CONFIG_PCI_MSI) - void (*rearm_msi)(struct gk20a *g); -#endif - void (*enable_shadow_rom)(struct gk20a *g); - void (*disable_shadow_rom)(struct gk20a *g); - u32 (*get_link_control_status)(struct gk20a *g); - void (*devinit_deferred_settings)(struct gk20a *g); - } xve; -#endif - struct gops_falcon falcon; - struct { - int (*fbp_init_support)(struct gk20a *g); - } fbp; - struct gops_priv_ring priv_ring; - struct { - int (*init)(struct gk20a *g); - u32 (*get_link_reset_mask)(struct gk20a *g); - int (*discover_link)(struct gk20a *g); - int (*rxdet)(struct gk20a *g, u32 link_id); - void (*get_connected_link_mask)(u32 *link_mask); - void (*set_sw_war)(struct gk20a *g, u32 link_id); - int (*configure_ac_coupling)(struct gk20a *g, - unsigned long mask, bool sync); - void (*prog_alt_clk)(struct gk20a *g); - void (*clear_link_reset)(struct gk20a *g, u32 link_id); - void (*enable_link_an0)(struct gk20a *g, u32 link_id); - /* API */ - struct { - int (*setup_pll)(struct gk20a *g, - unsigned long link_mask); - int (*data_ready_en)(struct gk20a *g, - unsigned long link_mask, bool sync); - u32 (*get_link_state)(struct gk20a *g, u32 link_id); - enum nvgpu_nvlink_link_mode (*get_link_mode)( - struct gk20a *g, - u32 link_id); - int (*set_link_mode)(struct gk20a *g, u32 link_id, - enum nvgpu_nvlink_link_mode mode); - u32 (*get_rx_sublink_state)(struct gk20a *g, - u32 link_id); - u32 (*get_tx_sublink_state)(struct gk20a *g, - u32 link_id); - enum nvgpu_nvlink_sublink_mode (*get_sublink_mode)( - struct gk20a *g, u32 link_id, - bool is_rx_sublink); - int (*set_sublink_mode)(struct gk20a *g, u32 link_id, - bool is_rx_sublink, - enum nvgpu_nvlink_sublink_mode mode); - } link_mode_transitions; - int (*reg_init)(struct gk20a *g); - struct { - u32 (*base_addr)(struct gk20a *g); - bool (*is_running)(struct gk20a *g); - int (*is_boot_complete)(struct gk20a *g, - bool *boot_cmplte); - u32 (*get_dlcmd_ordinal)(struct gk20a *g, - enum nvgpu_nvlink_minion_dlcmd dlcmd); - int (*send_dlcmd)(struct gk20a *g, u32 link_id, - enum nvgpu_nvlink_minion_dlcmd dlcmd, - bool sync); - void (*clear_intr)(struct gk20a *g); - void (*init_intr)(struct gk20a *g); - void (*enable_link_intr)(struct gk20a *g, u32 link_id, - bool enable); - void (*falcon_isr)(struct gk20a *g); - void (*isr)(struct gk20a *g); - bool (*is_debug_mode)(struct gk20a *g); - } minion; - struct { - void (*init_link_err_intr)(struct gk20a *g, u32 link_id); - void (*enable_link_err_intr)(struct gk20a *g, - u32 link_id, bool enable); - void (*isr)(struct gk20a *g); - } intr; - } nvlink; - struct gops_top top; - struct { - int (*init_sec2_setup_sw)(struct gk20a *g); - int (*init_sec2_support)(struct gk20a *g); - int (*sec2_destroy)(struct gk20a *g); - void (*secured_sec2_start)(struct gk20a *g); - void (*enable_irq)(struct nvgpu_sec2 *sec2, bool enable); - bool (*is_interrupted)(struct nvgpu_sec2 *sec2); - u32 (*get_intr)(struct gk20a *g); - bool (*msg_intr_received)(struct gk20a *g); - void (*set_msg_intr)(struct gk20a *g); - void (*clr_intr)(struct gk20a *g, u32 intr); - void (*process_intr)(struct gk20a *g, struct nvgpu_sec2 *sec2); - void (*msgq_tail)(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 *tail, bool set); - u32 (*falcon_base_addr)(void); - int (*sec2_reset)(struct gk20a *g); - int (*sec2_copy_to_emem)(struct gk20a *g, u32 dst, - u8 *src, u32 size, u8 port); - int (*sec2_copy_from_emem)(struct gk20a *g, - u32 src, u8 *dst, u32 size, u8 port); - int (*sec2_queue_head)(struct gk20a *g, - u32 queue_id, u32 queue_index, - u32 *head, bool set); - int (*sec2_queue_tail)(struct gk20a *g, - u32 queue_id, u32 queue_index, - u32 *tail, bool set); - void (*flcn_setup_boot_config)(struct gk20a *g); - } sec2; - struct { - u32 (*falcon_base_addr)(void); - void (*falcon_setup_boot_config)(struct gk20a *g); - int (*gsp_reset)(struct gk20a *g); - } gsp; -#ifdef CONFIG_NVGPU_TPC_POWERGATE - struct { - int (*init_tpc_powergate)(struct gk20a *g, u32 fuse_status); - void (*tpc_gr_pg)(struct gk20a *g); - } tpc; -#endif - void (*semaphore_wakeup)(struct gk20a *g, bool post_events); - - struct gops_grmgr grmgr; - -}; - /** * @brief HW version info read from the HW. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/acr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/acr.h new file mode 100644 index 000000000..6956fbf9e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/acr.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_ACR_H +#define NVGPU_GOPS_ACR_H + +struct gops_acr { + int (*acr_init)(struct gk20a *g); + int (*acr_construct_execute)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_ACR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/bios.h b/drivers/gpu/nvgpu/include/nvgpu/gops/bios.h new file mode 100644 index 000000000..d4dd6133b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/bios.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_BIOS_H +#define NVGPU_GOPS_BIOS_H + +struct gops_bios { + int (*bios_sw_init)(struct gk20a *g); + void (*bios_sw_deinit)(struct gk20a *g, + struct nvgpu_bios *bios); + u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i); + bool (*wait_for_bios_init_done)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_BIOS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h b/drivers/gpu/nvgpu/include/nvgpu/gops/bus.h similarity index 98% rename from drivers/gpu/nvgpu/include/nvgpu/gops_bus.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/bus.h index 01aa9cd04..5424b19f7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_bus.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/bus.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/cbc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/cbc.h new file mode 100644 index 000000000..f80f62747 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/cbc.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_CBC_H +#define NVGPU_GOPS_CBC_H + +#ifdef CONFIG_NVGPU_COMPRESSION +struct gops_cbc { + int (*cbc_init_support)(struct gk20a *g); + void (*cbc_remove_support)(struct gk20a *g); + void (*init)(struct gk20a *g, struct nvgpu_cbc *cbc); + u64 (*get_base_divisor)(struct gk20a *g); + int (*alloc_comptags)(struct gk20a *g, + struct nvgpu_cbc *cbc); + int (*ctrl)(struct gk20a *g, enum nvgpu_cbc_op op, + u32 min, u32 max); + u32 (*fix_config)(struct gk20a *g, int base); +}; +#endif + +#endif /* NVGPU_GOPS_CBC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ce.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ce.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ce.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_cg.h b/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_cg.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/cg.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_channel.h b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h similarity index 98% rename from drivers/gpu/nvgpu/include/nvgpu/gops_channel.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/channel.h index c557f472b..85860f85e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_class.h b/drivers/gpu/nvgpu/include/nvgpu/gops/class.h similarity index 97% rename from drivers/gpu/nvgpu/include/nvgpu/gops_class.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/class.h index d6778e930..8edede67f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_class.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/class.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/clk.h b/drivers/gpu/nvgpu/include/nvgpu/gops/clk.h new file mode 100644 index 000000000..b0bc31873 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/clk.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_CLK_H +#define NVGPU_GOPS_CLK_H + +#include + +struct gk20a; +struct namemap_cfg; +struct clk_gk20a; + +struct gops_clk { + int (*init_debugfs)(struct gk20a *g); + int (*init_clk_support)(struct gk20a *g); + void (*suspend_clk_support)(struct gk20a *g); + u32 (*get_crystal_clk_hz)(struct gk20a *g); + int (*clk_domain_get_f_points)(struct gk20a *g, + u32 clkapidomain, u32 *pfpointscount, + u16 *pfreqpointsinmhz); + int (*clk_get_round_rate)(struct gk20a *g, u32 api_domain, + unsigned long rate_target, unsigned long *rounded_rate); + int (*get_clk_range)(struct gk20a *g, u32 api_domain, + u16 *min_mhz, u16 *max_mhz); + unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain); + u32 (*get_rate_cntr)(struct gk20a *g, struct namemap_cfg *c); + u32 (*get_cntr_xbarclk_source)(struct gk20a *g); + u32 (*get_cntr_sysclk_source)(struct gk20a *g); + unsigned long (*get_rate)(struct gk20a *g, u32 api_domain); + int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate); + unsigned long (*get_fmax_at_vmin_safe)(struct gk20a *g); + u32 (*get_ref_clock_rate)(struct gk20a *g); + int (*predict_mv_at_hz_cur_tfloor)(struct clk_gk20a *clk, + unsigned long rate); + unsigned long (*get_maxrate)(struct gk20a *g, u32 api_domain); + int (*prepare_enable)(struct clk_gk20a *clk); + void (*disable_unprepare)(struct clk_gk20a *clk); + int (*get_voltage)(struct clk_gk20a *clk, u64 *val); + int (*get_gpcclk_clock_counter)(struct clk_gk20a *clk, u64 *val); + int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val); + int (*get_pll_debug_data)(struct gk20a *g, + struct nvgpu_clk_pll_debug_data *d); + int (*mclk_init)(struct gk20a *g); + void (*mclk_deinit)(struct gk20a *g); + int (*mclk_change)(struct gk20a *g, u16 val); + void (*get_change_seq_time)(struct gk20a *g, s64 *change_time); + void (*change_host_clk_source)(struct gk20a *g); + u32 (*clk_mon_init_domains)(struct gk20a *g); + bool split_rail_support; + bool support_pmgr_domain; + bool support_lpwr_pg; + int (*perf_pmu_vfe_load)(struct gk20a *g); + bool support_vf_point; + u8 lut_num_entries; +}; + +struct gops_clk_mon { + int (*clk_mon_alloc_memory)(struct gk20a *g); + bool (*clk_mon_check_master_fault_status)(struct gk20a *g); + int (*clk_mon_check_status)(struct gk20a *g, + u32 domain_mask); + bool (*clk_mon_check_clk_good)(struct gk20a *g); + bool (*clk_mon_check_pll_lock)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_CLK_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/gops/clk_arb.h new file mode 100644 index 000000000..7d8b91ec8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/clk_arb.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_CLK_ARB_H +#define NVGPU_GOPS_CLK_ARB_H + +#ifdef CONFIG_NVGPU_CLK_ARB +struct gops_clk_arb { + int (*clk_arb_init_arbiter)(struct gk20a *g); + int (*arbiter_clk_init)(struct gk20a *g); + bool (*check_clk_arb_support)(struct gk20a *g); + u32 (*get_arbiter_clk_domains)(struct gk20a *g); + int (*get_arbiter_f_points)(struct gk20a *g, u32 api_domain, + u32 *num_points, u16 *freqs_in_mhz); + int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain, + u16 *min_mhz, u16 *max_mhz); + int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain, + u16 *default_mhz); + void (*clk_arb_run_arbiter_cb)(struct nvgpu_clk_arb *arb); + /* This function is inherently unsafe to call while + * arbiter is running arbiter must be blocked + * before calling this function + */ + u32 (*get_current_pstate)(struct gk20a *g); + void (*clk_arb_cleanup)(struct nvgpu_clk_arb *arb); + void (*stop_clk_arb_threads)(struct gk20a *g); +}; +#endif + +#endif /* NVGPU_GOPS_CLK_ARB_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/cyclestats.h b/drivers/gpu/nvgpu/include/nvgpu/gops/cyclestats.h new file mode 100644 index 000000000..783ba54fc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/cyclestats.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_CYCLESTATS_H +#define NVGPU_GOPS_CYCLESTATS_H + +#ifdef CONFIG_NVGPU_CYCLESTATS +struct gops_css { + int (*enable_snapshot)(struct nvgpu_channel *ch, + struct gk20a_cs_snapshot_client *client); + void (*disable_snapshot)(struct gk20a *g); + int (*check_data_available)(struct nvgpu_channel *ch, + u32 *pending, + bool *hw_overflow); + void (*set_handled_snapshots)(struct gk20a *g, u32 num); + u32 (*allocate_perfmon_ids)(struct gk20a_cs_snapshot *data, + u32 count); + u32 (*release_perfmon_ids)(struct gk20a_cs_snapshot *data, + u32 start, + u32 count); + int (*detach_snapshot)(struct nvgpu_channel *ch, + struct gk20a_cs_snapshot_client *client); + bool (*get_overflow_status)(struct gk20a *g); + u32 (*get_pending_snapshots)(struct gk20a *g); + u32 (*get_max_buffer_size)(struct gk20a *g); +}; +#endif + +#endif /* NVGPU_GOPS_CYCLESTATS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h new file mode 100644 index 000000000..89568f062 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_DEBUGGER_H +#define NVGPU_GOPS_DEBUGGER_H + +#ifdef CONFIG_NVGPU_DEBUGGER +struct gops_regops { + int (*exec_regops)(struct gk20a *g, + struct nvgpu_tsg *tsg, + struct nvgpu_dbg_reg_op *ops, + u32 num_ops, + u32 *flags); + const struct regop_offset_range* ( + *get_global_whitelist_ranges)(void); + u64 (*get_global_whitelist_ranges_count)(void); + const struct regop_offset_range* ( + *get_context_whitelist_ranges)(void); + u64 (*get_context_whitelist_ranges_count)(void); + const u32* (*get_runcontrol_whitelist)(void); + u64 (*get_runcontrol_whitelist_count)(void); +}; +struct gops_debugger { + void (*post_events)(struct nvgpu_channel *ch); + int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, + bool disable_powergate); +}; +struct gops_perf { + void (*enable_membuf)(struct gk20a *g, u32 size, u64 buf_addr); + void (*disable_membuf)(struct gk20a *g); + void (*init_inst_block)(struct gk20a *g, + struct nvgpu_mem *inst_block); + void (*deinit_inst_block)(struct gk20a *g); + void (*membuf_reset_streaming)(struct gk20a *g); + u32 (*get_membuf_pending_bytes)(struct gk20a *g); + void (*set_membuf_handled_bytes)(struct gk20a *g, + u32 entries, u32 entry_size); + bool (*get_membuf_overflow_status)(struct gk20a *g); + u32 (*get_pmm_per_chiplet_offset)(void); +}; +struct gops_perfbuf { + int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size); + int (*perfbuf_disable)(struct gk20a *g); + int (*init_inst_block)(struct gk20a *g); + void (*deinit_inst_block)(struct gk20a *g); +}; +#endif + +#endif /* NVGPU_GOPS_DEBUGGER_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ecc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ecc.h similarity index 97% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ecc.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ecc.h index 1ff9f162f..6c309320e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_ecc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ecc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_engine.h b/drivers/gpu/nvgpu/include/nvgpu/gops/engine.h similarity index 97% rename from drivers/gpu/nvgpu/include/nvgpu/gops_engine.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/engine.h index 5a5cfc4f3..dccea1f3f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_engine.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/engine.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_fb.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_fb.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/fb.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fbp.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fbp.h new file mode 100644 index 000000000..9636e88f6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fbp.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_FBP_H +#define NVGPU_GOPS_FBP_H + +struct gops_fbp { + int (*fbp_init_support)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_FBP_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_fifo.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/floorsweep.h b/drivers/gpu/nvgpu/include/nvgpu/gops/floorsweep.h new file mode 100644 index 000000000..61196720a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/floorsweep.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_FLOORSWEEP_H +#define NVGPU_GOPS_FLOORSWEEP_H + +#ifdef CONFIG_NVGPU_TPC_POWERGATE +struct gops_tpc { + int (*init_tpc_powergate)(struct gk20a *g, u32 fuse_status); + void (*tpc_gr_pg)(struct gk20a *g); +}; +#endif + +#endif /* NVGPU_GOPS_FLOORSWEEP_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/func.h b/drivers/gpu/nvgpu/include/nvgpu/gops/func.h new file mode 100644 index 000000000..1e636e467 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/func.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_FUNC_H +#define NVGPU_GOPS_FUNC_H + +struct gops_func { + u32 (*get_full_phys_offset)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_FUNC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_fuse.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_fuse.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_gr.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/gr.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_grmgr.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h new file mode 100644 index 000000000..c9ff16210 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_GSP_H +#define NVGPU_GOPS_GSP_H + +#include + +struct gk20a; + +struct gops_gsp { + u32 (*falcon_base_addr)(void); + void (*falcon_setup_boot_config)(struct gk20a *g); + int (*gsp_reset)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_GSP_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_mc.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/mc.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h new file mode 100644 index 000000000..1b6bbade4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mm.h @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GOPS_MM_H +#define NVGPU_GOPS_MM_H + +/** + * @file + * + * MM HAL interface. + */ + +#include + +struct gk20a; + +/** + * This structure describes the HAL functions related to + * GMMU fault handling. + */ +struct gops_mm_mmu_fault { + /** + * @brief HAL to initialize the software setup of + * GMMU fault buffer. + * + * @param g [in] The GPU. + * + * Initializes the software setup of GMMU fault buffer: + * - Initializes the hub isr mutex to avoid race during + * GMMU fault buffer read/write handling from + * nvgpu software side. + * - Allocates memory to store the non replayable + * GMMU fault information. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure case: + * - Insufficient system memory (ENOMEM). + */ + int (*setup_sw)(struct gk20a *g); + + /** + * @brief HAL to initialize the hardware setup of + * GMMU fault buffer. + * + * @param g [in] The GPU. + * + * Initializes the hardware setup of GMMU fault buffer: + * - Configures the GMMU fault buffer base address and its + * size information in fbhubmmu specific BAR0 register. + */ + void (*setup_hw)(struct gk20a *g); + + /** + * @brief HAL to free the GMMU fault buffer. + * + * @param g [in] The GPU. + * + * Free the GMMU fault buffer: + * - Free the GMMU fault buffer memory. + * - Destroy the hub isr mutex. + */ + void (*info_mem_destroy)(struct gk20a *g); + + /** + * @brief HAL to disable the hardware setup of GMMU + * fault buffer. + * + * @param g [in] The GPU. + * + * Disable the hardware setup of GMMU fault buffer. + */ + void (*disable_hw)(struct gk20a *g); + + /** + * @brief HAL to parse mmu fault info read from h/w. + * + * @param mmufault [in] Pointer to memory containing info + * to be parsed. + * + */ + void (*parse_mmu_fault_info)(struct mmu_fault_info *mmufault); +}; + +/** + * This structure describes the HAL functions related to + * fb and L2 hardware operations. + */ +struct gops_mm_cache { + /** + * @brief HAL to flush the frame buffer memory. + * + * @param g [in] The GPU. + * + * Flush the frame buffer memory: + * - Flushes the FB. Then, waits for completion (by polling) + * upto polling timeout. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure case: + * - CPU polling timeout during FB flush operation (-EBUSY). + */ + int (*fb_flush)(struct gk20a *g); + + /** + * @brief HAL to invalidate the L2. + * + * @param g [in] The GPU. + * + * Invalidate the L2: + * - Trigger the L2 invalidate operation. Then, waits for + * completion (by polling) upto polling timeout. + * + * Note: It does not return error. But CPU polling can timeout. + */ + void (*l2_invalidate)(struct gk20a *g); + + /** + * @brief HAL to flush and invalidate the L2 and fb. + * + * @param g [in] The GPU. + * @param invalidate [in] true if L2 invalidate is also + * required. + * + * Flush and invalidate the L2 and fb: + * - Trigger the fb flush operation. Then, waits for completion + * (by polling) upto polling timeout. + * - Trigger the L2 invalidate operation. Then, waits for + * completion (by polling) upto polling timeout. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure cases: + * - CPU polling timeout during FB flush operation (-EBUSY). + * - CPU polling timeout during L2 invalidate operation + * (-EBUSY). + */ + int (*l2_flush)(struct gk20a *g, bool invalidate); +#ifdef CONFIG_NVGPU_COMPRESSION + /** + * @brief HAL to flush Compression Bit Cache memory. + * + * @param g [in] The GPU. + * + * Flush and invalidate the L2 and fb: + * - Trigger all dirty lines from the CBC to L2. + * Then, waits for completion (by polling) upto + * polling timeout. + * + * Note: It does not return error. But CPU polling can timeout. + */ + void (*cbc_clean)(struct gk20a *g); +#endif +}; + +/** + * This structure describes the HAL functions related to + * GMMU operations. + */ +struct gops_mm_gmmu { + /** + * @brief HAL to get the GMMU level mapping info structure. + * + * @param g [in] The GPU. + * @param big_page_size [in] Big page size supported by GMMU. + * + * @return Pointer to GMMU level mapping info structure. + */ + const struct gk20a_mmu_level * + (*get_mmu_levels)(struct gk20a *g, u64 big_page_size); + + /** + * @brief HAL to get maximum page table levels supported by the + * GMMU HW. + * + * @param g [in] The GPU. + * + * @return Page table levels supported by GPU. + */ + u32 (*get_max_page_table_levels)(struct gk20a *g); + + /** + * @brief HAL functions for GMMU Map. + * + * @param vm [in] Pointer to virtual memory + * structure. + * @param map_offset [in] GPU virtual address. + * @param sgt [in] Pointer to scatter gather table + * for direct "physical" nvgpu_mem + * structures. + * @param buffer_offset [in] Offset address from start of + * the memory. + * @param size [in] Size of the buffer in bytes. + * @param pgsz_idx [in] Index into the page size table. + * - Min: GMMU_PAGE_SIZE_SMALL + * - Max: GMMU_PAGE_SIZE_KERNEL + * @param kind_v [in] Kind attributes for mapping. + * @param ctag_offset [in] Size of the buffer in bytes. + * @param flags [in] Mapping flags. + * Min:NVGPU_VM_MAP_FIXED_OFFSET + * Max:NVGPU_VM_MAP_PLATFORM_ATOMIC + * @param rw_flag [in] Flag designates the requested + * GMMU mapping. + * @param clear_ctags [in] True if ctags clear is required. + * @param sparse [in] True if the mapping should be + * sparse. + * @param priv [in] True if the mapping should be + * privileged. + * @param batch [in] Mapping_batch handle. Structure + * which track whether the L2 flush + * and TLB invalidate are required + * or not during map/unmap. + * @param aperture [in] Where the memory actually was + * allocated from. + * + * Locked version of GMMU Map routine: + * - Decodes the Mapping flags, rw_flag, priv and aperture for + * GMMU mapping. + * - Allocates a new GPU VA range for a specific size + * if vaddr is 0. + * #nvgpu_vm_alloc_va() reserves the GPU VA. + * - Program PDE and PTE entry with PA/IPA, mapping flags, + * rw_flag and aperture information. + * #nvgpu_gmmu_update_page_table does the pde and pte updates. + * - Chip specific stuff is handled at the PTE/PDE + * programming HAL layer. + * GMMU level entry format will be different for each + * GPU family (i.e, gv11b, gp10b). + * - Invalidates the GPU TLB, gm20b_fb_tlb_invalidate does the + * tlb invalidate. + * + * @return valid GMMU VA start address in case of success. + * @return 0 in case of all possible failures. + * Possible Failure cases: + * - No free GPU VA space (GPU VA space full). + * - TLB invalidate timeout. + */ + u64 (*map)(struct vm_gk20a *vm, + u64 map_offset, + struct nvgpu_sgt *sgt, + u64 buffer_offset, + u64 size, + u32 pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + enum gk20a_mem_rw_flag rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch, + enum nvgpu_aperture aperture); + + /** + * @brief HAL functions for GMMU Unmap. + * + * @param vm [in] Pointer to virtual memory + * structure. + * @param vaddr [in] GPU virtual address. + * @param size [in] Size of the buffer in bytes. + * @param pgsz_idx [in] Index into the page size table. + * - Min: GMMU_PAGE_SIZE_SMALL + * - Max: GMMU_PAGE_SIZE_KERNEL + * @param va_allocated [in] Indicates if gpu_va address is + * valid/allocated. + * @param rw_flag [in] Flag designates the requested + * GMMU mapping. + * @param sparse [in] True if the mapping should be + * sparse. + * @param batch [in] Mapping_batch handle. Structure + * which track whether the L2 flush + * and TLB invalidate are required + * or not during map/unmap. + * + * Locked version of GMMU Unmap routine: + * - Free the reserved GPU VA space staring at @gpu_va. + * #nvgpu_vm_free_va does free the GPU VA space. + * - Program PDE and PTE entry with default information which is + * internally frees up the GPU VA space. + * - Chip specific stuff is handled at the PTE/PDE + * programming HAL layer. + * GMMU level entry format will be different for + * each GPU family (i.e, gv11b). + * - Flush the GPU L2. gv11b_mm_l2_flush does the L2 flush. + * - Invalidates the GPU TLB, #gm20b_fb_tlb_invalidate() does + * the tlb invalidate. + */ + void (*unmap)(struct vm_gk20a *vm, + u64 vaddr, + u64 size, + u32 pgsz_idx, + bool va_allocated, + enum gk20a_mem_rw_flag rw_flag, + bool sparse, + struct vm_gk20a_mapping_batch *batch); + + /** + * @brief HAL to get the available big page sizes. + * + * @param g [in] The GPU. + * + * Get the available big page sizes: + * - Bitwise OR of all available big page sizes. + * - Big page size will be different for each GPU family + * (i.e. gv11b, tu104). + * + * @return Valid bitwise OR of all available big page sizes + * if big page support is enabled. + * @return 0 if big page support is disabled. + */ + u32 (*get_big_page_sizes)(void); + + /** + * @brief HAL to get the default big page size in bytes. + * + * @param g [in] The GPU. + * + * Default big page size: + * - Big page size will be different for each GPU family + * (i.e. gv11b, tu104). + * + * @return Valid big page size if big page support is enabled. + * @return 0 if big page support is disabled. + */ + u32 (*get_default_big_page_size)(void); + + /** + * @brief HAL to get the iommu physical bit position. + * + * @param g [in] The GPU. + * + * This HAL is used to get the iommu physical bit position. + * + * @return iommu physical bit position. + */ + u32 (*get_iommu_bit)(struct gk20a *g); + + /** + * @brief HAL to convert from tegra_phys to gpu_phys. + * + * @param g [in] The GPU. + * @param attrs [in] Pointer to gmmu attributes. + * @param phys [in] Tegra physical address. + * + * This HAL is used to convert from tegra_phys to gpu_phys + * for GMMU programming. + * + * Notes: + * On Volta the GPU determines whether to do L3 allocation + * for a mapping by checking bit 36 of the phsyical address. + * So if a mapping should allocate lines in the L3 then + * this bit must be set. + * + * @return gpu physical address for GMMU programming. + */ + u64 (*gpu_phys_addr)(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, + u64 phys); +}; + +struct gops_mm { + /** + * @brief HAL to initialize an internal structure which is used to + * track pd_cache. + * + * @param g [in] The GPU. + * + * Initialize the pd_cache: + * - Allocates the zero initialized memory area for #nvgpu_pd_cache. + * - Initializes the mutexes and list nodes for pd_cache + * tracking. + * + * @return 0 in case of success. + * @return -ENOMEM (< 0) in case of failure. + * Possible failure case: + * - Insufficient system memory (ENOMEM). + */ + int (*pd_cache_init)(struct gk20a *g); + + /** + * @brief HAL to initialize the Memory Management unit. + * + * @param g [in] The GPU. + * + * MM init: + * - MM S/W init: + * - Resets the current pramin window index to 0. + * - Initializes the vidmem page allocator with size, flags and etc. + * - Allocates vidmem memory for acr blob from bootstrap region. + * - Creates the CE vidmem clear thread for vidmem clear operations + * during vidmem free. + * - Allocates memory for sysmem flush operation. + * - Initializes the GMMU virtual memory region for BAR1. + * - Allocates and initializes the BAR1 instance block. + * - Initializes the GMMU virtual memory region for PMU. + * - Allocates and initializes the PMU instance block. + * - Initializes the GMMU virtual memory region for CE. + * - Allocates the GMMU debug write and read buffer (4K size). + * - MM H/W setup: + * - Configures the GMMU debug buffer location in fbhubmmu register. + * - Enables the fbhubmmu mc interrupt. + * - Binds the BAR1 inst block and checks whether the bind + * operation is successful. + * - Flushes the FB. Then, waits for completion (by polling) + * upto polling timeout. + * - Configures the GMMU fault buffer location in fbhubmmu register. + * + * @return 0 in case of success, < 0 in case of failure. + * @retval Error returned by setup_sw and setup_hw routines. + * Possible failure cases: + * - Insufficient system memory (ENOMEM). + * - CPU polling timeout during FB flush operation (-EBUSY). + */ + int (*init_mm_support)(struct gk20a *g); + + /** + * @brief HAL to suspend the Memory Management unit. + * + * @param g [in] The GPU. + * + * Suspend MM unit: + * - Pause the CE vidmem clear thread. + * - Flushes the FB and L2. Then, waits for completion (by polling) + * upto polling timeout. + * - Invalidate L2. + * - Disable the fbhubmmu mc interrupt. + * - Disable the mmu fault buffer h/w setup. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure case: + * - CPU polling timeout during FB or L2 flush operation (-EBUSY). + */ + int (*mm_suspend)(struct gk20a *g); + + /** + * @brief HAL to bind the virtual memory context to the given channel. + * + * @param vm [in] Pointer to virtual memory context. + * @param ch [in] Pointer to nvgpu_channel. + * + * Bind a channel: + * - Increment reference count of virtual memory context. + * - Assign the virtual memory context to channel's virtual + * memory context. + * - Program the different hardware blocks of GPU with addresses + * associated with virtual memory context. + * + * @return 0, always. + */ + int (*vm_bind_channel)(struct vm_gk20a *vm, struct nvgpu_channel *ch); + + /** + * @brief HAL to setup the Memory Management hardware. + * + * @param g [in] The GPU. + * + * MM hardware setup: + * - Configures the GMMU debug buffer location in fbhubmmu register. + * - Enables the fbhubmmu mc interrupt. + * - Binds the BAR1 inst block and checks whether the bind + * operation is successful. + * - Flushes the FB. Then, waits for completion (by polling) + * upto polling timeout. + * - Configures the GMMU fault buffer location in fbhubmmu register. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure cases: + * - Insufficient system memory (ENOMEM). + * - CPU polling timeout during FB flush operation (-EBUSY). + */ + int (*setup_hw)(struct gk20a *g); + + /** + * @brief HAL to get the BAR1 aperture availability status. + * + * @param g [in] The GPU. + * + * BAR1 status: + * - false for gv11b. + * + * @return True if BAR1 aperture support is available. + * @return False if BAR1 aperture support is not available. + */ + bool (*is_bar1_supported)(struct gk20a *g); + + /** + * @brief HAL to initialize the BAR2 virtual memory. + * + * @param g [in] The GPU. + * + * Initialize BAR2: + * - Initializes the GMMU virtual memory region for BAR2. + * - Allocates and initializes the BAR2 instance block. + * + * @return 0 in case of success, < 0 in case of failure. + * Possible failure case: + * - Insufficient system memory (ENOMEM). + */ + int (*init_bar2_vm)(struct gk20a *g); + + /** + * @brief HAL to free the BAR2 virtual memory. + * + * @param g [in] The GPU. + * + * Free BAR2 VM: + * - Free the BAR2 instance block. + * - Free the BAR2 GMMU virtual memory region. + */ + void (*remove_bar2_vm)(struct gk20a *g); + + /** + * @brief HAL to initialize the instance block memory. + * + * @param inst_block [in] Pointer to instance block memory. + * @param vm [in] Pointer to virtual memory context. + * @param big_page_size [in] Big page size supported by GMMU. + * + * Initializes the instance block memory: + * - Configures the pdb base, big page size and + * sub context's pdb base in context's instance block memory. + */ + void (*init_inst_block)(struct nvgpu_mem *inst_block, + struct vm_gk20a *vm, u32 big_page_size); + + /** + * @brief HAL to get the maximum flush retry counts. + * + * @param g [in] The GPU. + * @param op [in] Requested operations on various unit. + * + * Get the maximum retry flush counts (retry timer) for the + * following operations: + * - Flush the Frame Buffer memory. + * - L2 Cache Flush. + * + * These retries are specific to GPU hardware and vary based on + * size of the frame buffer memory. + * + * @return Maximum flush retry counts for a specific h/w operation. + */ + u32 (*get_flush_retries)(struct gk20a *g, enum nvgpu_flush_op op); + + /** @cond DOXYGEN_SHOULD_SKIP_THIS */ + u64 (*bar1_map_userd)(struct gk20a *g, struct nvgpu_mem *mem, + u32 offset); + int (*vm_as_alloc_share)(struct gk20a *g, struct vm_gk20a *vm); + void (*vm_as_free_share)(struct vm_gk20a *vm); + /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ + + struct gops_mm_mmu_fault mmu_fault; + struct gops_mm_cache cache; + struct gops_mm_gmmu gmmu; +}; + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_netlist.h b/drivers/gpu/nvgpu/include/nvgpu/gops/netlist.h similarity index 95% rename from drivers/gpu/nvgpu/include/nvgpu/gops_netlist.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/netlist.h index e83d1fbcf..1487a0392 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_netlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/netlist.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h b/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h new file mode 100644 index 000000000..5832b1511 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/nvdec.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_NVDEC_H +#define NVGPU_GOPS_NVDEC_H + +struct gops_nvdec { + u32 (*falcon_base_addr)(void); +}; + +#endif /* NVGPU_GOPS_NVDEC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/gops/nvlink.h new file mode 100644 index 000000000..9fc4c6915 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/nvlink.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_NVLINK_H +#define NVGPU_GOPS_NVLINK_H + +/* API */ +struct gops_nvlink_link_mode_transitions { + int (*setup_pll)(struct gk20a *g, + unsigned long link_mask); + int (*data_ready_en)(struct gk20a *g, + unsigned long link_mask, bool sync); + u32 (*get_link_state)(struct gk20a *g, u32 link_id); + enum nvgpu_nvlink_link_mode (*get_link_mode)( + struct gk20a *g, + u32 link_id); + int (*set_link_mode)(struct gk20a *g, u32 link_id, + enum nvgpu_nvlink_link_mode mode); + u32 (*get_rx_sublink_state)(struct gk20a *g, + u32 link_id); + u32 (*get_tx_sublink_state)(struct gk20a *g, + u32 link_id); + enum nvgpu_nvlink_sublink_mode (*get_sublink_mode)( + struct gk20a *g, u32 link_id, + bool is_rx_sublink); + int (*set_sublink_mode)(struct gk20a *g, u32 link_id, + bool is_rx_sublink, + enum nvgpu_nvlink_sublink_mode mode); +}; + +struct gops_nvlink_minion { + u32 (*base_addr)(struct gk20a *g); + bool (*is_running)(struct gk20a *g); + int (*is_boot_complete)(struct gk20a *g, + bool *boot_cmplte); + u32 (*get_dlcmd_ordinal)(struct gk20a *g, + enum nvgpu_nvlink_minion_dlcmd dlcmd); + int (*send_dlcmd)(struct gk20a *g, u32 link_id, + enum nvgpu_nvlink_minion_dlcmd dlcmd, + bool sync); + void (*clear_intr)(struct gk20a *g); + void (*init_intr)(struct gk20a *g); + void (*enable_link_intr)(struct gk20a *g, u32 link_id, + bool enable); + void (*falcon_isr)(struct gk20a *g); + void (*isr)(struct gk20a *g); + bool (*is_debug_mode)(struct gk20a *g); +}; + +struct gops_nvlink_intr { + void (*init_link_err_intr)(struct gk20a *g, u32 link_id); + void (*enable_link_err_intr)(struct gk20a *g, + u32 link_id, bool enable); + void (*isr)(struct gk20a *g); +}; + +struct gops_nvlink { + int (*init)(struct gk20a *g); + u32 (*get_link_reset_mask)(struct gk20a *g); + int (*discover_link)(struct gk20a *g); + int (*rxdet)(struct gk20a *g, u32 link_id); + void (*get_connected_link_mask)(u32 *link_mask); + void (*set_sw_war)(struct gk20a *g, u32 link_id); + int (*configure_ac_coupling)(struct gk20a *g, + unsigned long mask, bool sync); + void (*prog_alt_clk)(struct gk20a *g); + void (*clear_link_reset)(struct gk20a *g, u32 link_id); + void (*enable_link_an0)(struct gk20a *g, u32 link_id); + /* API */ + struct gops_nvlink_link_mode_transitions link_mode_transitions; + int (*reg_init)(struct gk20a *g); + struct gops_nvlink_minion minion; + struct gops_nvlink_intr intr; +}; + +#endif /* NVGPU_GOPS_NVLINK_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_pbdma.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h similarity index 99% rename from drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h index 80e0ed322..8e1036faa 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h @@ -29,6 +29,10 @@ struct gk20a; struct nvgpu_pmu; struct nvgpu_hw_err_inject_info_desc; +struct gops_pmu_perf { + int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); +}; + /** * PMU unit and engine HAL operations. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pramin.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pramin.h new file mode 100644 index 000000000..047854bf3 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pramin.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_PRAMIN_H +#define NVGPU_GOPS_PRAMIN_H + +struct gops_pramin { + u32 (*data032_r)(u32 i); +}; + +#endif /* NVGPU_GOPS_PRAMIN_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_priv_ring.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/profiler.h b/drivers/gpu/nvgpu/include/nvgpu/gops/profiler.h new file mode 100644 index 000000000..659698506 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/profiler.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_PROFILER_H +#define NVGPU_GOPS_PROFILER_H + +#ifdef CONFIG_NVGPU_PROFILER +struct gops_pm_reservation { + int (*acquire)(struct gk20a *g, u32 reservation_id, + enum nvgpu_profiler_pm_resource_type pm_resource, + enum nvgpu_profiler_pm_reservation_scope scope, + u32 vmid); + int (*release)(struct gk20a *g, u32 reservation_id, + enum nvgpu_profiler_pm_resource_type pm_resource, + u32 vmid); + void (*release_all_per_vmid)(struct gk20a *g, u32 vmid); +}; +#endif + +#endif /* NVGPU_GOPS_PROFILER_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h similarity index 98% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ptimer.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h index abb185f6c..1b6e0f2b5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ramfc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ramfc.h similarity index 96% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ramfc.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ramfc.h index 224df12bf..2121025cc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_ramfc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ramfc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ramin.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h similarity index 98% rename from drivers/gpu/nvgpu/include/nvgpu/gops_ramin.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h index 6b84e4aed..b0a96ca34 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_ramin.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_runlist.h b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_runlist.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/sbr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/sbr.h new file mode 100644 index 000000000..67df384d9 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/sbr.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_SBR_H +#define NVGPU_GOPS_SBR_H + +struct gops_sbr { + int (*sbr_pub_load_and_execute)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_SBR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/gops/sec2.h new file mode 100644 index 000000000..830d8a0fd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/sec2.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_SEC2_H +#define NVGPU_GOPS_SEC2_H + +#include + +struct gk20a; + +struct gops_sec2 { + int (*init_sec2_setup_sw)(struct gk20a *g); + int (*init_sec2_support)(struct gk20a *g); + int (*sec2_destroy)(struct gk20a *g); + void (*secured_sec2_start)(struct gk20a *g); + void (*enable_irq)(struct nvgpu_sec2 *sec2, bool enable); + bool (*is_interrupted)(struct nvgpu_sec2 *sec2); + u32 (*get_intr)(struct gk20a *g); + bool (*msg_intr_received)(struct gk20a *g); + void (*set_msg_intr)(struct gk20a *g); + void (*clr_intr)(struct gk20a *g, u32 intr); + void (*process_intr)(struct gk20a *g, struct nvgpu_sec2 *sec2); + void (*msgq_tail)(struct gk20a *g, struct nvgpu_sec2 *sec2, + u32 *tail, bool set); + u32 (*falcon_base_addr)(void); + int (*sec2_reset)(struct gk20a *g); + int (*sec2_copy_to_emem)(struct gk20a *g, u32 dst, + u8 *src, u32 size, u8 port); + int (*sec2_copy_from_emem)(struct gk20a *g, + u32 src, u8 *dst, u32 size, u8 port); + int (*sec2_queue_head)(struct gk20a *g, + u32 queue_id, u32 queue_index, + u32 *head, bool set); + int (*sec2_queue_tail)(struct gk20a *g, + u32 queue_id, u32 queue_index, + u32 *tail, bool set); + void (*flcn_setup_boot_config)(struct gk20a *g); +}; + +#endif /* NVGPU_GOPS_SEC2_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_sync.h b/drivers/gpu/nvgpu/include/nvgpu/gops/sync.h similarity index 50% rename from drivers/gpu/nvgpu/include/nvgpu/gops_sync.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/sync.h index 225839fc5..e4784eb08 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_sync.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/sync.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,6 +37,67 @@ struct vm_gk20a; struct priv_cmd_entry; struct nvgpu_semaphore; +struct gops_sync_syncpt { + /** + * @brief Map syncpoint aperture as read-only. + * + * @param vm [in] VM area for channel. + * @param base_gpu [out] Base GPU VA for mapped + * syncpoint aperture. + * @param sync_size [out] Size of syncpoint aperture + * in bytes. + * + * Map syncpoint aperture in GPU virtual memory as read-only: + * - Acquire syncpoint read-only map lock. + * - Map syncpoint aperture in sysmem to GPU virtual memory, + * if not already mapped. Map as read-only. + * - Release syncpoint read-only map lock. + * + * @return 0 in case of success, < 0 in case of failure. + * @retval -ENOMEM if syncpoint aperture could not be + * mapped to GPU virtual memory. + */ + int (*get_sync_ro_map)(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); + +/** @cond DOXYGEN_SHOULD_SKIP_THIS */ + int (*alloc_buf)(struct nvgpu_channel *c, + u32 syncpt_id, + struct nvgpu_mem *syncpt_buf); + void (*free_buf)(struct nvgpu_channel *c, + struct nvgpu_mem *syncpt_buf); +#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT + void (*add_wait_cmd)(struct gk20a *g, + struct priv_cmd_entry *cmd, + u32 id, u32 thresh, u64 gpu_va_base); + u32 (*get_wait_cmd_size)(void); + void (*add_incr_cmd)(struct gk20a *g, + struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va, + bool wfi); + u32 (*get_incr_cmd_size)(bool wfi_cmd); + u32 (*get_incr_per_release)(void); +#endif +/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ +}; + +#if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \ + defined(CONFIG_NVGPU_SW_SEMAPHORE) +/** @cond DOXYGEN_SHOULD_SKIP_THIS */ +struct gops_sync_sema { + u32 (*get_wait_cmd_size)(void); + u32 (*get_incr_cmd_size)(void); + void (*add_wait_cmd)(struct gk20a *g, + struct priv_cmd_entry *cmd, + struct nvgpu_semaphore *s, u64 sema_va); + void (*add_incr_cmd)(struct gk20a *g, + struct priv_cmd_entry *cmd, + struct nvgpu_semaphore *s, u64 sema_va, + bool wfi); +}; +/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ +#endif + /** * Sync HAL operations. * @@ -44,66 +105,12 @@ struct nvgpu_semaphore; */ struct gops_sync { #ifdef CONFIG_TEGRA_GK20A_NVHOST - struct gops_sync_syncpt { - /** - * @brief Map syncpoint aperture as read-only. - * - * @param vm [in] VM area for channel. - * @param base_gpu [out] Base GPU VA for mapped - * syncpoint aperture. - * @param sync_size [out] Size of syncpoint aperture - * in bytes. - * - * Map syncpoint aperture in GPU virtual memory as read-only: - * - Acquire syncpoint read-only map lock. - * - Map syncpoint aperture in sysmem to GPU virtual memory, - * if not already mapped. Map as read-only. - * - Release syncpoint read-only map lock. - * - * @return 0 in case of success, < 0 in case of failure. - * @retval -ENOMEM if syncpoint aperture could not be - * mapped to GPU virtual memory. - */ - int (*get_sync_ro_map)(struct vm_gk20a *vm, - u64 *base_gpuva, u32 *sync_size); - -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ - int (*alloc_buf)(struct nvgpu_channel *c, - u32 syncpt_id, - struct nvgpu_mem *syncpt_buf); - void (*free_buf)(struct nvgpu_channel *c, - struct nvgpu_mem *syncpt_buf); -#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT - void (*add_wait_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, - u32 id, u32 thresh, u64 gpu_va_base); - u32 (*get_wait_cmd_size)(void); - void (*add_incr_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va, - bool wfi); - u32 (*get_incr_cmd_size)(bool wfi_cmd); - u32 (*get_incr_per_release)(void); -#endif -/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ - } syncpt; - + struct gops_sync_syncpt syncpt; #endif /* CONFIG_TEGRA_GK20A_NVHOST */ - #if defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) && \ defined(CONFIG_NVGPU_SW_SEMAPHORE) /** @cond DOXYGEN_SHOULD_SKIP_THIS */ - struct gops_sync_sema { - u32 (*get_wait_cmd_size)(void); - u32 (*get_incr_cmd_size)(void); - void (*add_wait_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, - struct nvgpu_semaphore *s, u64 sema_va); - void (*add_incr_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, - struct nvgpu_semaphore *s, u64 sema_va, - bool wfi); - } sema; + struct gops_sync_sema sema; /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_therm.h b/drivers/gpu/nvgpu/include/nvgpu/gops/therm.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_therm.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/therm.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_top.h b/drivers/gpu/nvgpu/include/nvgpu/gops/top.h similarity index 100% rename from drivers/gpu/nvgpu/include/nvgpu/gops_top.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/top.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_tsg.h b/drivers/gpu/nvgpu/include/nvgpu/gops/tsg.h similarity index 97% rename from drivers/gpu/nvgpu/include/nvgpu/gops_tsg.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/tsg.h index 1d62b00c0..7b106b088 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/tsg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_userd.h b/drivers/gpu/nvgpu/include/nvgpu/gops/userd.h similarity index 96% rename from drivers/gpu/nvgpu/include/nvgpu/gops_userd.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/userd.h index 5ed60c07f..8a1aa9ff1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_userd.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/userd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_usermode.h b/drivers/gpu/nvgpu/include/nvgpu/gops/usermode.h similarity index 97% rename from drivers/gpu/nvgpu/include/nvgpu/gops_usermode.h rename to drivers/gpu/nvgpu/include/nvgpu/gops/usermode.h index 36b96d867..bf2145ed0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_usermode.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/usermode.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/xve.h b/drivers/gpu/nvgpu/include/nvgpu/gops/xve.h new file mode 100644 index 000000000..73ee58acb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/xve.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_XVE_H +#define NVGPU_GOPS_XVE_H + +#ifdef CONFIG_NVGPU_DGPU +struct gops_xve { + int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); + int (*set_speed)(struct gk20a *g, u32 xve_link_speed); + void (*available_speeds)(struct gk20a *g, u32 *speed_mask); + u32 (*xve_readl)(struct gk20a *g, u32 reg); + void (*xve_writel)(struct gk20a *g, u32 reg, u32 val); + void (*disable_aspm)(struct gk20a *g); + void (*reset_gpu)(struct gk20a *g); +#if defined(CONFIG_PCI_MSI) + void (*rearm_msi)(struct gk20a *g); +#endif + void (*enable_shadow_rom)(struct gk20a *g); + void (*disable_shadow_rom)(struct gk20a *g); + u32 (*get_link_control_status)(struct gk20a *g); + void (*devinit_deferred_settings)(struct gk20a *g); +}; +#endif + +#endif /* NVGPU_GOPS_XVE_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_mm.h b/drivers/gpu/nvgpu/include/nvgpu/gops_mm.h deleted file mode 100644 index 838efd127..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_mm.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_GOPS_MM_H -#define NVGPU_GOPS_MM_H - -/** - * @file - * - * MM HAL interface. - */ - -#include - -struct gk20a; - -struct gops_mm { - /** - * @brief HAL to initialize an internal structure which is used to - * track pd_cache. - * - * @param g [in] The GPU. - * - * Initialize the pd_cache: - * - Allocates the zero initialized memory area for #nvgpu_pd_cache. - * - Initializes the mutexes and list nodes for pd_cache - * tracking. - * - * @return 0 in case of success. - * @return -ENOMEM (< 0) in case of failure. - * Possible failure case: - * - Insufficient system memory (ENOMEM). - */ - int (*pd_cache_init)(struct gk20a *g); - - /** - * @brief HAL to initialize the Memory Management unit. - * - * @param g [in] The GPU. - * - * MM init: - * - MM S/W init: - * - Resets the current pramin window index to 0. - * - Initializes the vidmem page allocator with size, flags and etc. - * - Allocates vidmem memory for acr blob from bootstrap region. - * - Creates the CE vidmem clear thread for vidmem clear operations - * during vidmem free. - * - Allocates memory for sysmem flush operation. - * - Initializes the GMMU virtual memory region for BAR1. - * - Allocates and initializes the BAR1 instance block. - * - Initializes the GMMU virtual memory region for PMU. - * - Allocates and initializes the PMU instance block. - * - Initializes the GMMU virtual memory region for CE. - * - Allocates the GMMU debug write and read buffer (4K size). - * - MM H/W setup: - * - Configures the GMMU debug buffer location in fbhubmmu register. - * - Enables the fbhubmmu mc interrupt. - * - Binds the BAR1 inst block and checks whether the bind - * operation is successful. - * - Flushes the FB. Then, waits for completion (by polling) - * upto polling timeout. - * - Configures the GMMU fault buffer location in fbhubmmu register. - * - * @return 0 in case of success, < 0 in case of failure. - * @retval Error returned by setup_sw and setup_hw routines. - * Possible failure cases: - * - Insufficient system memory (ENOMEM). - * - CPU polling timeout during FB flush operation (-EBUSY). - */ - int (*init_mm_support)(struct gk20a *g); - - /** - * @brief HAL to suspend the Memory Management unit. - * - * @param g [in] The GPU. - * - * Suspend MM unit: - * - Pause the CE vidmem clear thread. - * - Flushes the FB and L2. Then, waits for completion (by polling) - * upto polling timeout. - * - Invalidate L2. - * - Disable the fbhubmmu mc interrupt. - * - Disable the mmu fault buffer h/w setup. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure case: - * - CPU polling timeout during FB or L2 flush operation (-EBUSY). - */ - int (*mm_suspend)(struct gk20a *g); - - /** - * @brief HAL to bind the virtual memory context to the given channel. - * - * @param vm [in] Pointer to virtual memory context. - * @param ch [in] Pointer to nvgpu_channel. - * - * Bind a channel: - * - Increment reference count of virtual memory context. - * - Assign the virtual memory context to channel's virtual - * memory context. - * - Program the different hardware blocks of GPU with addresses - * associated with virtual memory context. - * - * @return 0, always. - */ - int (*vm_bind_channel)(struct vm_gk20a *vm, struct nvgpu_channel *ch); - - /** - * @brief HAL to setup the Memory Management hardware. - * - * @param g [in] The GPU. - * - * MM hardware setup: - * - Configures the GMMU debug buffer location in fbhubmmu register. - * - Enables the fbhubmmu mc interrupt. - * - Binds the BAR1 inst block and checks whether the bind - * operation is successful. - * - Flushes the FB. Then, waits for completion (by polling) - * upto polling timeout. - * - Configures the GMMU fault buffer location in fbhubmmu register. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure cases: - * - Insufficient system memory (ENOMEM). - * - CPU polling timeout during FB flush operation (-EBUSY). - */ - int (*setup_hw)(struct gk20a *g); - - /** - * @brief HAL to get the BAR1 aperture availability status. - * - * @param g [in] The GPU. - * - * BAR1 status: - * - false for gv11b. - * - * @return True if BAR1 aperture support is available. - * @return False if BAR1 aperture support is not available. - */ - bool (*is_bar1_supported)(struct gk20a *g); - - /** - * @brief HAL to initialize the BAR2 virtual memory. - * - * @param g [in] The GPU. - * - * Initialize BAR2: - * - Initializes the GMMU virtual memory region for BAR2. - * - Allocates and initializes the BAR2 instance block. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure case: - * - Insufficient system memory (ENOMEM). - */ - int (*init_bar2_vm)(struct gk20a *g); - - /** - * @brief HAL to free the BAR2 virtual memory. - * - * @param g [in] The GPU. - * - * Free BAR2 VM: - * - Free the BAR2 instance block. - * - Free the BAR2 GMMU virtual memory region. - */ - void (*remove_bar2_vm)(struct gk20a *g); - - /** - * @brief HAL to initialize the instance block memory. - * - * @param inst_block [in] Pointer to instance block memory. - * @param vm [in] Pointer to virtual memory context. - * @param big_page_size [in] Big page size supported by GMMU. - * - * Initializes the instance block memory: - * - Configures the pdb base, big page size and - * sub context's pdb base in context's instance block memory. - */ - void (*init_inst_block)(struct nvgpu_mem *inst_block, - struct vm_gk20a *vm, u32 big_page_size); - - /** - * @brief HAL to get the maximum flush retry counts. - * - * @param g [in] The GPU. - * @param op [in] Requested operations on various unit. - * - * Get the maximum retry flush counts (retry timer) for the - * following operations: - * - Flush the Frame Buffer memory. - * - L2 Cache Flush. - * - * These retries are specific to GPU hardware and vary based on - * size of the frame buffer memory. - * - * @return Maximum flush retry counts for a specific h/w operation. - */ - u32 (*get_flush_retries)(struct gk20a *g, enum nvgpu_flush_op op); - - /** @cond DOXYGEN_SHOULD_SKIP_THIS */ - u64 (*bar1_map_userd)(struct gk20a *g, struct nvgpu_mem *mem, - u32 offset); - int (*vm_as_alloc_share)(struct gk20a *g, struct vm_gk20a *vm); - void (*vm_as_free_share)(struct vm_gk20a *vm); - /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ - - /** - * This structure describes the HAL functions related to - * GMMU fault handling. - */ - struct gops_mm_mmu_fault { - /** - * @brief HAL to initialize the software setup of - * GMMU fault buffer. - * - * @param g [in] The GPU. - * - * Initializes the software setup of GMMU fault buffer: - * - Initializes the hub isr mutex to avoid race during - * GMMU fault buffer read/write handling from - * nvgpu software side. - * - Allocates memory to store the non replayable - * GMMU fault information. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure case: - * - Insufficient system memory (ENOMEM). - */ - int (*setup_sw)(struct gk20a *g); - - /** - * @brief HAL to initialize the hardware setup of - * GMMU fault buffer. - * - * @param g [in] The GPU. - * - * Initializes the hardware setup of GMMU fault buffer: - * - Configures the GMMU fault buffer base address and its - * size information in fbhubmmu specific BAR0 register. - */ - void (*setup_hw)(struct gk20a *g); - - /** - * @brief HAL to free the GMMU fault buffer. - * - * @param g [in] The GPU. - * - * Free the GMMU fault buffer: - * - Free the GMMU fault buffer memory. - * - Destroy the hub isr mutex. - */ - void (*info_mem_destroy)(struct gk20a *g); - - /** - * @brief HAL to disable the hardware setup of GMMU - * fault buffer. - * - * @param g [in] The GPU. - * - * Disable the hardware setup of GMMU fault buffer. - */ - void (*disable_hw)(struct gk20a *g); - - /** - * @brief HAL to parse mmu fault info read from h/w. - * - * @param mmufault [in] Pointer to memory containing info - * to be parsed. - * - */ - void (*parse_mmu_fault_info)(struct mmu_fault_info *mmufault); - - } mmu_fault; - - /** - * This structure describes the HAL functions related to - * fb and L2 hardware operations. - */ - struct gops_mm_cache { - /** - * @brief HAL to flush the frame buffer memory. - * - * @param g [in] The GPU. - * - * Flush the frame buffer memory: - * - Flushes the FB. Then, waits for completion (by polling) - * upto polling timeout. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure case: - * - CPU polling timeout during FB flush operation (-EBUSY). - */ - int (*fb_flush)(struct gk20a *g); - - /** - * @brief HAL to invalidate the L2. - * - * @param g [in] The GPU. - * - * Invalidate the L2: - * - Trigger the L2 invalidate operation. Then, waits for - * completion (by polling) upto polling timeout. - * - * Note: It does not return error. But CPU polling can timeout. - */ - void (*l2_invalidate)(struct gk20a *g); - - /** - * @brief HAL to flush and invalidate the L2 and fb. - * - * @param g [in] The GPU. - * @param invalidate [in] true if L2 invalidate is also - * required. - * - * Flush and invalidate the L2 and fb: - * - Trigger the fb flush operation. Then, waits for completion - * (by polling) upto polling timeout. - * - Trigger the L2 invalidate operation. Then, waits for - * completion (by polling) upto polling timeout. - * - * @return 0 in case of success, < 0 in case of failure. - * Possible failure cases: - * - CPU polling timeout during FB flush operation (-EBUSY). - * - CPU polling timeout during L2 invalidate operation - * (-EBUSY). - */ - int (*l2_flush)(struct gk20a *g, bool invalidate); -#ifdef CONFIG_NVGPU_COMPRESSION - /** - * @brief HAL to flush Compression Bit Cache memory. - * - * @param g [in] The GPU. - * - * Flush and invalidate the L2 and fb: - * - Trigger all dirty lines from the CBC to L2. - * Then, waits for completion (by polling) upto - * polling timeout. - * - * Note: It does not return error. But CPU polling can timeout. - */ - void (*cbc_clean)(struct gk20a *g); -#endif - } cache; - - /** - * This structure describes the HAL functions related to - * GMMU operations. - */ - struct gops_mm_gmmu { - /** - * @brief HAL to get the GMMU level mapping info structure. - * - * @param g [in] The GPU. - * @param big_page_size [in] Big page size supported by GMMU. - * - * @return Pointer to GMMU level mapping info structure. - */ - const struct gk20a_mmu_level * - (*get_mmu_levels)(struct gk20a *g, u64 big_page_size); - - /** - * @brief HAL to get maximum page table levels supported by the - * GMMU HW. - * - * @param g [in] The GPU. - * - * @return Page table levels supported by GPU. - */ - u32 (*get_max_page_table_levels)(struct gk20a *g); - - /** - * @brief HAL functions for GMMU Map. - * - * @param vm [in] Pointer to virtual memory - * structure. - * @param map_offset [in] GPU virtual address. - * @param sgt [in] Pointer to scatter gather table - * for direct "physical" nvgpu_mem - * structures. - * @param buffer_offset [in] Offset address from start of - * the memory. - * @param size [in] Size of the buffer in bytes. - * @param pgsz_idx [in] Index into the page size table. - * - Min: GMMU_PAGE_SIZE_SMALL - * - Max: GMMU_PAGE_SIZE_KERNEL - * @param kind_v [in] Kind attributes for mapping. - * @param ctag_offset [in] Size of the buffer in bytes. - * @param flags [in] Mapping flags. - * Min:NVGPU_VM_MAP_FIXED_OFFSET - * Max:NVGPU_VM_MAP_PLATFORM_ATOMIC - * @param rw_flag [in] Flag designates the requested - * GMMU mapping. - * @param clear_ctags [in] True if ctags clear is required. - * @param sparse [in] True if the mapping should be - * sparse. - * @param priv [in] True if the mapping should be - * privileged. - * @param batch [in] Mapping_batch handle. Structure - * which track whether the L2 flush - * and TLB invalidate are required - * or not during map/unmap. - * @param aperture [in] Where the memory actually was - * allocated from. - * - * Locked version of GMMU Map routine: - * - Decodes the Mapping flags, rw_flag, priv and aperture for - * GMMU mapping. - * - Allocates a new GPU VA range for a specific size - * if vaddr is 0. - * #nvgpu_vm_alloc_va() reserves the GPU VA. - * - Program PDE and PTE entry with PA/IPA, mapping flags, - * rw_flag and aperture information. - * #nvgpu_gmmu_update_page_table does the pde and pte updates. - * - Chip specific stuff is handled at the PTE/PDE - * programming HAL layer. - * GMMU level entry format will be different for each - * GPU family (i.e, gv11b, gp10b). - * - Invalidates the GPU TLB, gm20b_fb_tlb_invalidate does the - * tlb invalidate. - * - * @return valid GMMU VA start address in case of success. - * @return 0 in case of all possible failures. - * Possible Failure cases: - * - No free GPU VA space (GPU VA space full). - * - TLB invalidate timeout. - */ - u64 (*map)(struct vm_gk20a *vm, - u64 map_offset, - struct nvgpu_sgt *sgt, - u64 buffer_offset, - u64 size, - u32 pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture); - - /** - * @brief HAL functions for GMMU Unmap. - * - * @param vm [in] Pointer to virtual memory - * structure. - * @param vaddr [in] GPU virtual address. - * @param size [in] Size of the buffer in bytes. - * @param pgsz_idx [in] Index into the page size table. - * - Min: GMMU_PAGE_SIZE_SMALL - * - Max: GMMU_PAGE_SIZE_KERNEL - * @param va_allocated [in] Indicates if gpu_va address is - * valid/allocated. - * @param rw_flag [in] Flag designates the requested - * GMMU mapping. - * @param sparse [in] True if the mapping should be - * sparse. - * @param batch [in] Mapping_batch handle. Structure - * which track whether the L2 flush - * and TLB invalidate are required - * or not during map/unmap. - * - * Locked version of GMMU Unmap routine: - * - Free the reserved GPU VA space staring at @gpu_va. - * #nvgpu_vm_free_va does free the GPU VA space. - * - Program PDE and PTE entry with default information which is - * internally frees up the GPU VA space. - * - Chip specific stuff is handled at the PTE/PDE - * programming HAL layer. - * GMMU level entry format will be different for - * each GPU family (i.e, gv11b). - * - Flush the GPU L2. gv11b_mm_l2_flush does the L2 flush. - * - Invalidates the GPU TLB, #gm20b_fb_tlb_invalidate() does - * the tlb invalidate. - */ - void (*unmap)(struct vm_gk20a *vm, - u64 vaddr, - u64 size, - u32 pgsz_idx, - bool va_allocated, - enum gk20a_mem_rw_flag rw_flag, - bool sparse, - struct vm_gk20a_mapping_batch *batch); - - /** - * @brief HAL to get the available big page sizes. - * - * @param g [in] The GPU. - * - * Get the available big page sizes: - * - Bitwise OR of all available big page sizes. - * - Big page size will be different for each GPU family - * (i.e. gv11b, tu104). - * - * @return Valid bitwise OR of all available big page sizes - * if big page support is enabled. - * @return 0 if big page support is disabled. - */ - u32 (*get_big_page_sizes)(void); - - /** - * @brief HAL to get the default big page size in bytes. - * - * @param g [in] The GPU. - * - * Default big page size: - * - Big page size will be different for each GPU family - * (i.e. gv11b, tu104). - * - * @return Valid big page size if big page support is enabled. - * @return 0 if big page support is disabled. - */ - u32 (*get_default_big_page_size)(void); - - /** - * @brief HAL to get the iommu physical bit position. - * - * @param g [in] The GPU. - * - * This HAL is used to get the iommu physical bit position. - * - * @return iommu physical bit position. - */ - u32 (*get_iommu_bit)(struct gk20a *g); - - /** - * @brief HAL to convert from tegra_phys to gpu_phys. - * - * @param g [in] The GPU. - * @param attrs [in] Pointer to gmmu attributes. - * @param phys [in] Tegra physical address. - * - * This HAL is used to convert from tegra_phys to gpu_phys - * for GMMU programming. - * - * Notes: - * On Volta the GPU determines whether to do L3 allocation - * for a mapping by checking bit 36 of the phsyical address. - * So if a mapping should allocate lines in the L3 then - * this bit must be set. - * - * @return gpu physical address for GMMU programming. - */ - u64 (*gpu_phys_addr)(struct gk20a *g, - struct nvgpu_gmmu_attrs *attrs, - u64 phys); - } gmmu; -}; - -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h b/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h new file mode 100644 index 000000000..1fc464dd0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_OPS_H +#define NVGPU_GOPS_OPS_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gk20a; +struct nvgpu_debug_context; +struct nvgpu_mem; + +struct gops_debug { + void (*show_dump)(struct gk20a *g, + struct nvgpu_debug_context *o); +}; + +/** + * @addtogroup unit-common-nvgpu + * @{ + */ + +/** + * @brief HAL methods + * + * gpu_ops contains function pointers for the unit HAL interfaces. gpu_ops + * should only contain function pointers! Non-function pointer members should go + * in struct gk20a or be implemented with the boolean flag API defined in + * nvgpu/enabled.h. Each unit should have its own sub-struct in the gpu_ops + * struct. + */ +struct gpu_ops { + + struct gops_acr acr; + struct gops_sbr sbr; + struct gops_func func; + struct gops_ecc ecc; + struct gops_ltc ltc; +#ifdef CONFIG_NVGPU_COMPRESSION + struct gops_cbc cbc; +#endif + struct gops_ce ce; + struct gops_gr gr; + struct gops_class gpu_class; + struct gops_fb fb; + struct gops_nvdec nvdec; + struct gops_cg cg; + struct gops_fifo fifo; + struct gops_fuse fuse; + struct gops_ramfc ramfc; + struct gops_ramin ramin; + struct gops_runlist runlist; + struct gops_userd userd; + struct gops_engine engine; + struct gops_pbdma pbdma; + struct gops_sync sync; + struct gops_channel channel; + struct gops_tsg tsg; + struct gops_usermode usermode; + struct gops_engine_status engine_status; + struct gops_pbdma_status pbdma_status; + struct gops_netlist netlist; + struct gops_mm mm; + /* + * This function is called to allocate secure memory (memory + * that the CPU cannot see). The function should fill the + * context buffer descriptor (especially fields destroy, sgt, + * size). + */ + int (*secure_alloc)(struct gk20a *g, struct nvgpu_mem *desc_mem, + size_t size, + void (**fn)(struct gk20a *g, struct nvgpu_mem *mem)); + +#ifdef CONFIG_NVGPU_DGPU + struct gops_pramin pramin; +#endif + struct gops_therm therm; + struct gops_pmu pmu; + struct gops_clk clk; +#ifdef CONFIG_NVGPU_DGPU + struct gops_clk_mon clk_mon; +#endif +#ifdef CONFIG_NVGPU_CLK_ARB + struct gops_clk_arb clk_arb; +#endif + struct gops_pmu_perf pmu_perf; +#ifdef CONFIG_NVGPU_DEBUGGER + struct gops_regops regops; +#endif + struct gops_mc mc; + struct gops_debug debug; +#ifdef CONFIG_NVGPU_DEBUGGER + struct gops_debugger debugger; + struct gops_perf perf; + struct gops_perfbuf perfbuf; +#endif +#ifdef CONFIG_NVGPU_PROFILER + struct gops_pm_reservation pm_reservation; +#endif + + u32 (*get_litter_value)(struct gk20a *g, int value); + int (*chip_init_gpu_characteristics)(struct gk20a *g); + + struct gops_bus bus; + struct gops_ptimer ptimer; + struct gops_bios bios; +#ifdef CONFIG_NVGPU_CYCLESTATS + struct gops_css css; +#endif +#ifdef CONFIG_NVGPU_DGPU + struct gops_xve xve; +#endif + struct gops_falcon falcon; + struct gops_fbp fbp; + struct gops_priv_ring priv_ring; + struct gops_nvlink nvlink; + struct gops_top top; + struct gops_sec2 sec2; + struct gops_gsp gsp; +#ifdef CONFIG_NVGPU_TPC_POWERGATE + struct gops_tpc tpc; +#endif + void (*semaphore_wakeup)(struct gk20a *g, bool post_events); + + struct gops_grmgr grmgr; + +}; + +#endif /* NVGPU_GOPS_OPS_H */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h index 8c2b2417d..d1c728631 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h @@ -88,7 +88,7 @@ * ------------- * Most of the static interfaces are HAL functions. They are documented * here. - * + include/nvgpu/gops_mc.h + * + include/nvgpu/gops/mc.h * * Dynamic Design * ============== @@ -105,7 +105,7 @@ * ------------- * Some of the dynamic interfaces are HAL functions. They are documented * here. - * + include/nvgpu/gops_mc.h + * + include/nvgpu/gops/mc.h * * Following interface is common function. * + nvgpu_wait_for_deferred_interrupts() diff --git a/drivers/gpu/nvgpu/os/linux/intr.c b/drivers/gpu/nvgpu/os/linux/intr.c index baecb1621..f227f8578 100644 --- a/drivers/gpu/nvgpu/os/linux/intr.c +++ b/drivers/gpu/nvgpu/os/linux/intr.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "os_linux.h" diff --git a/userspace/units/init/nvgpu-init.c b/userspace/units/init/nvgpu-init.c index 5a1525fe3..9c98f3115 100644 --- a/userspace/units/init/nvgpu-init.c +++ b/userspace/units/init/nvgpu-init.c @@ -32,7 +32,6 @@ #include #include #include -#include /* for get_litter testing */ #include "hal/init/hal_gv11b_litter.h" diff --git a/userspace/units/mm/mm/mm.c b/userspace/units/mm/mm/mm.c index f7d205443..d1c499d26 100644 --- a/userspace/units/mm/mm/mm.c +++ b/userspace/units/mm/mm/mm.c @@ -27,7 +27,6 @@ #include #include -#include #include "os/posix/os_posix.h" diff --git a/userspace/units/mm/page_table_faults/page_table_faults.c b/userspace/units/mm/page_table_faults/page_table_faults.c index 5097baec1..87328bc1a 100644 --- a/userspace/units/mm/page_table_faults/page_table_faults.c +++ b/userspace/units/mm/page_table_faults/page_table_faults.c @@ -35,7 +35,6 @@ #include #include #include -#include #include "os/posix/os_posix.h" #include "hal/fifo/channel_gv11b.h"