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gpu: nvgpu: more nvgpu_memcpy changes

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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs to
qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches over non-offending memcpy() uses in gr/pmu/volt
code to nvgpu_memcpy() with appropriate casts applied to maintain
consistency within the nvgpu source base.

Also fixed a Rule 8.3 violation in vfe_var.c by sync'ing the param
names between declarations of the devinit_get_vfe_var_table()
routine.

JIRA NVGPU-849

Change-Id: I004b461988bd3a26212b6fbf660ee7fa742ea1ba
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1952984
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2018-11-17 10:57:18 -08:00
committed by mobile promotions
parent 692841ca56
commit 38dee046b0
3 changed files with 17 additions and 16 deletions
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8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -3882,10 +3882,10 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
struct zbc_entry zbc_val; struct zbc_entry zbc_val;
zbc_val.type = GK20A_ZBC_TYPE_COLOR; zbc_val.type = GK20A_ZBC_TYPE_COLOR;
(void) memcpy(zbc_val.color_ds, nvgpu_memcpy((u8 *)zbc_val.color_ds,
c_tbl->color_ds, sizeof(zbc_val.color_ds)); (u8 *)c_tbl->color_ds, sizeof(zbc_val.color_ds));
(void) memcpy(zbc_val.color_l2, nvgpu_memcpy((u8 *)zbc_val.color_l2,
c_tbl->color_l2, sizeof(zbc_val.color_l2)); (u8 *)c_tbl->color_l2, sizeof(zbc_val.color_l2));
zbc_val.format = c_tbl->format; zbc_val.format = c_tbl->format;
ret = g->ops.gr.add_zbc_color(g, gr, &zbc_val, i); ret = g->ops.gr.add_zbc_color(g, gr, &zbc_val, i);

14
drivers/gpu/nvgpu/pmu_perf/vfe_var.c
View File

@@ -33,7 +33,7 @@
#include "vfe_var.h" #include "vfe_var.h"
static int devinit_get_vfe_var_table(struct gk20a *g, static int devinit_get_vfe_var_table(struct gk20a *g,
struct vfe_vars *pvfevarobjs); struct vfe_vars *pvarobjs);
static int vfe_var_construct_single(struct gk20a *g, static int vfe_var_construct_single(struct gk20a *g,
struct boardobj **ppboardobj, struct boardobj **ppboardobj,
u16 size, void *pargs); u16 size, void *pargs);
@@ -609,16 +609,16 @@ static int _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g,
pset = (struct nv_pmu_vfe_var_single_sensed_fuse *) pset = (struct nv_pmu_vfe_var_single_sensed_fuse *)
ppmudata; ppmudata;
(void) memcpy(&pset->vfield_info, nvgpu_memcpy((u8 *)&pset->vfield_info,
&pvfe_var_single_sensed_fuse->vfield_info, (u8 *)&pvfe_var_single_sensed_fuse->vfield_info,
sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info)); sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info));
(void) memcpy(&pset->vfield_ver_info, nvgpu_memcpy((u8 *)&pset->vfield_ver_info,
&pvfe_var_single_sensed_fuse->vfield_ver_info, (u8 *)&pvfe_var_single_sensed_fuse->vfield_ver_info,
sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info)); sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info));
(void) memcpy(&pset->override_info, nvgpu_memcpy((u8 *)&pset->override_info,
&pvfe_var_single_sensed_fuse->override_info, (u8 *)&pvfe_var_single_sensed_fuse->override_info,
sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_override_info)); sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_override_info));
pset->b_fuse_value_signed = pvfe_var_single_sensed_fuse->b_fuse_value_signed; pset->b_fuse_value_signed = pvfe_var_single_sensed_fuse->b_fuse_value_signed;

11
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -27,6 +27,7 @@
#include <nvgpu/boardobjgrp_e32.h> #include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmuif/ctrlvolt.h> #include <nvgpu/pmuif/ctrlvolt.h>
#include <nvgpu/pmuif/ctrlperf.h> #include <nvgpu/pmuif/ctrlperf.h>
#include <nvgpu/string.h>
#include "pmu_perf/pmu_perf.h" #include "pmu_perf/pmu_perf.h"
#include "gp106/bios_gp106.h" #include "gp106/bios_gp106.h"
@@ -257,8 +258,8 @@ static int volt_policy_set_voltage(struct gk20a *g, u8 client_id,
/* Set RPC parameters. */ /* Set RPC parameters. */
rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE; rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE;
rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx; rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx;
(void) memcpy(&rpc_call.params.volt_policy_voltage_data.rail_list, nvgpu_memcpy((u8 *)&rpc_call.params.volt_policy_voltage_data.rail_list,
prail_list, (sizeof(struct ctrl_perf_volt_rail_list))); (u8 *)prail_list, (sizeof(struct ctrl_perf_volt_rail_list)));
/* Execute the voltage change request via PMU RPC. */ /* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call); status = volt_pmu_rpc_execute(g, &rpc_call);
@@ -353,9 +354,9 @@ static int volt_policy_set_noiseaware_vmin(struct gk20a *g,
rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN; rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN;
rpc_call.params.volt_rail_set_noise_unaware_vmin.num_rails = rpc_call.params.volt_rail_set_noise_unaware_vmin.num_rails =
prail_list->num_rails; prail_list->num_rails;
(void) memcpy( nvgpu_memcpy(
&rpc_call.params.volt_rail_set_noise_unaware_vmin.rail_list, (u8 *)&rpc_call.params.volt_rail_set_noise_unaware_vmin.rail_list,
prail_list, (sizeof(struct ctrl_volt_volt_rail_list))); (u8 *)prail_list, (sizeof(struct ctrl_volt_volt_rail_list)));
/* Execute the voltage change request via PMU RPC. */ /* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call); status = volt_pmu_rpc_execute(g, &rpc_call);