From 390695e67ebf951ba35497f7cbc185aff17220fb Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Fri, 2 Aug 2019 13:53:38 -0400 Subject: [PATCH] gpu: nvgpu: ptimer: fix CERT-C violations Rule INT30-C requires that unsigned integer operations do not wrap. Fix these violations by using the safe ops. Rule INT31-C requires that integer conversions do not result in lost or misinterpreted data. Rule INT33-C requires ensurance that division does not divide by 0. Fix violations of these types in ptimer. JIRA NVGPU-3868 Change-Id: Ib513da20eb14fa058630aa7a1f0aa5002373dd08 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2168575 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/ptimer.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h index 5ca27fbad..9c1825b69 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h @@ -23,6 +23,7 @@ #define NVGPU_PTIMER_H #include +#include struct gk20a; @@ -37,12 +38,14 @@ struct nvgpu_cpu_time_correlation_sample { static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) { - return U32((U64(PTIMER_REF_FREQ_HZ) * U64(10)) / U64(ptimer_src_freq)); + return nvgpu_safe_cast_u64_to_u32((U64(PTIMER_REF_FREQ_HZ) * U64(10)) + / U64(ptimer_src_freq)); } static inline u32 scale_ptimer(u32 timeout , u32 scale10x) { - if (((timeout*10U) % scale10x) >= (scale10x/2U)) { + nvgpu_assert(scale10x != 0U); + if ((nvgpu_safe_mult_u32(timeout, 10U) % scale10x) >= (scale10x/2U)) { return ((timeout * 10U) / scale10x) + 1U; } else { return (timeout * 10U) / scale10x;