From 39070c653f9c31bedf2eb4f428bb8924829f5d5b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 25 Apr 2019 15:31:36 -0700 Subject: [PATCH] gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h Move and rename FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID JIRA NVGPU-2012 Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2109011 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fence/fence.c | 3 ++- drivers/gpu/nvgpu/common/fifo/channel.c | 4 ++-- drivers/gpu/nvgpu/common/fifo/engines.c | 20 +++++++++---------- drivers/gpu/nvgpu/common/fifo/tsg.c | 4 ++-- drivers/gpu/nvgpu/common/gr/gr_intr.c | 12 +++++------ drivers/gpu/nvgpu/common/rc/rc.c | 2 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 8 -------- drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c | 2 +- .../gpu/nvgpu/hal/fifo/ctxsw_timeout_gk20a.c | 2 +- .../gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b.c | 8 ++++---- drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c | 2 +- drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c | 2 +- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c | 11 +++++----- .../nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c | 6 +++--- drivers/gpu/nvgpu/hal/rc/rc_gk20a.c | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/channel.h | 2 ++ .../nvgpu/include/nvgpu/channel_sync_syncpt.h | 4 +++- drivers/gpu/nvgpu/include/nvgpu/engines.h | 2 ++ drivers/gpu/nvgpu/include/nvgpu/runlist.h | 2 ++ drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 3 ++- 20 files changed, 52 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fence/fence.c b/drivers/gpu/nvgpu/common/fence/fence.c index 36bea080b..39e801b6a 100644 --- a/drivers/gpu/nvgpu/common/fence/fence.c +++ b/drivers/gpu/nvgpu/common/fence/fence.c @@ -29,6 +29,7 @@ #include #include #include +#include static struct nvgpu_fence_type *nvgpu_fence_from_ref(struct nvgpu_ref *ref) { @@ -191,7 +192,7 @@ void nvgpu_fence_init(struct nvgpu_fence_type *f, return; } f->ops = ops; - f->syncpt_id = FIFO_INVAL_SYNCPT_ID; + f->syncpt_id = NVGPU_INVALID_SYNCPT_ID; f->semaphore = NULL; f->os_fence = os_fence; } diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 7ff7b099d..594da7784 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -623,7 +623,7 @@ void _gk20a_channel_put(struct channel_gk20a *ch, const char *caller) struct channel_gk20a *_gk20a_channel_from_id(struct gk20a *g, u32 chid, const char *caller) { - if (chid == FIFO_INVAL_CHANNEL_ID) { + if (chid == NVGPU_INVALID_CHANNEL_ID) { return NULL; } @@ -1141,7 +1141,7 @@ int nvgpu_channel_set_syncpt(struct channel_gk20a *ch) new_syncpt = nvgpu_channel_sync_get_syncpt_id(sync_syncpt); } else { - new_syncpt = FIFO_INVAL_SYNCPT_ID; + new_syncpt = NVGPU_INVALID_SYNCPT_ID; } } diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 20c4b255e..1174bbc34 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -165,7 +165,7 @@ bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id) u32 nvgpu_engine_get_gr_id(struct gk20a *g) { u32 gr_engine_cnt = 0; - u32 gr_engine_id = FIFO_INVAL_ENGINE_ID; + u32 gr_engine_id = NVGPU_INVALID_ENG_ID; /* Consider 1st available GR engine */ gr_engine_cnt = nvgpu_engine_get_ids(g, &gr_engine_id, @@ -280,8 +280,8 @@ int nvgpu_engine_disable_activity(struct gk20a *g, struct nvgpu_engine_info *eng_info, bool wait_for_idle) { - u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID; - u32 engine_chid = FIFO_INVAL_CHANNEL_ID; + u32 pbdma_chid = NVGPU_INVALID_CHANNEL_ID; + u32 engine_chid = NVGPU_INVALID_CHANNEL_ID; u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = -EINVAL; struct channel_gk20a *ch = NULL; @@ -316,7 +316,7 @@ int nvgpu_engine_disable_activity(struct gk20a *g, pbdma_chid = pbdma_status.next_id; } - if (pbdma_chid != FIFO_INVAL_CHANNEL_ID) { + if (pbdma_chid != NVGPU_INVALID_CHANNEL_ID) { ch = gk20a_channel_from_id(g, pbdma_chid); if (ch != NULL) { err = g->ops.fifo.preempt_channel(g, ch); @@ -338,7 +338,7 @@ int nvgpu_engine_disable_activity(struct gk20a *g, engine_chid = engine_status.ctx_next_id; } - if (engine_chid != FIFO_INVAL_ENGINE_ID && engine_chid != pbdma_chid) { + if (engine_chid != NVGPU_INVALID_ENG_ID && engine_chid != pbdma_chid) { ch = gk20a_channel_from_id(g, engine_chid); if (ch != NULL) { err = g->ops.fifo.preempt_channel(g, ch); @@ -605,7 +605,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) u32 nvgpu_engine_get_gr_runlist_id(struct gk20a *g) { u32 gr_engine_cnt = 0; - u32 gr_engine_id = FIFO_INVAL_ENGINE_ID; + u32 gr_engine_id = NVGPU_INVALID_ENG_ID; struct nvgpu_engine_info *engine_info; u32 gr_runlist_id = U32_MAX; @@ -665,7 +665,7 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) */ u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id) { - u32 fault_id = FIFO_INVAL_ENGINE_ID; + u32 fault_id = NVGPU_INVALID_ENG_ID; struct nvgpu_engine_info *engine_info; engine_info = nvgpu_engine_get_active_eng_info(g, engine_id); @@ -693,7 +693,7 @@ u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id) if (engine_info->fault_id == fault_id) { break; } - active_engine_id = FIFO_INVAL_ENGINE_ID; + active_engine_id = NVGPU_INVALID_ENG_ID; } return active_engine_id; } @@ -827,7 +827,7 @@ u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, u32 id = U32_MAX; bool is_tsg = false; u32 mailbox2; - u32 act_eng_id = FIFO_INVAL_ENGINE_ID; + u32 act_eng_id = NVGPU_INVALID_ENG_ID; struct nvgpu_engine_status_info engine_status; for (engine_id = 0U; engine_id < g->fifo.num_engines; engine_id++) { @@ -845,7 +845,7 @@ u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, nvgpu_engine_status_is_ctxsw(&engine_status); if (!failing_engine) { - act_eng_id = FIFO_INVAL_ENGINE_ID; + act_eng_id = NVGPU_INVALID_ENG_ID; continue; } diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 05cd5c690..504df7612 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -103,7 +103,7 @@ int nvgpu_tsg_bind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch) } /* all the channel part of TSG should need to be same runlist_id */ - if (tsg->runlist_id == FIFO_INVAL_TSG_ID) { + if (tsg->runlist_id == NVGPU_INVALID_TSG_ID) { tsg->runlist_id = ch->runlist_id; } else if (tsg->runlist_id != ch->runlist_id) { nvgpu_err(tsg->g, @@ -644,7 +644,7 @@ int nvgpu_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg, pid_t pid) tsg->vm = NULL; tsg->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW; tsg->timeslice_us = g->ops.tsg.default_timeslice_us(g); - tsg->runlist_id = FIFO_INVAL_TSG_ID; + tsg->runlist_id = NVGPU_INVALID_TSG_ID; tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; tsg->gr_ctx = nvgpu_alloc_gr_ctx_struct(g); if (tsg->gr_ctx == NULL) { diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c index beba7c59d..145f1cce4 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr.c +++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c @@ -171,7 +171,7 @@ static int gr_intr_handle_class_error(struct gk20a *g, struct nvgpu_gr_isr_data *isr_data) { u32 chid = isr_data->ch != NULL ? - isr_data->ch->chid : FIFO_INVAL_CHANNEL_ID; + isr_data->ch->chid : NVGPU_INVALID_CHANNEL_ID; nvgpu_log_fn(g, " "); @@ -199,7 +199,7 @@ static void gr_intr_report_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, tsgid = NVGPU_INVALID_TSG_ID; curr_ctx = g->ops.gr.falcon.get_current_ctx(g); ch = nvgpu_gr_intr_get_channel_from_ctx(g, curr_ctx, &tsgid); - chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID; + chid = ch != NULL ? ch->chid : NVGPU_INVALID_CHANNEL_ID; if (ch != NULL) { gk20a_channel_put(ch); } @@ -325,7 +325,7 @@ void nvgpu_gr_intr_report_exception(struct gk20a *g, u32 inst, tsgid = NVGPU_INVALID_TSG_ID; curr_ctx = g->ops.gr.falcon.get_current_ctx(g); ch = nvgpu_gr_intr_get_channel_from_ctx(g, curr_ctx, &tsgid); - chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID; + chid = ch != NULL ? ch->chid : NVGPU_INVALID_CHANNEL_ID; if (ch != NULL) { gk20a_channel_put(ch); } @@ -480,7 +480,7 @@ int nvgpu_gr_intr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, int ret = 0; struct nvgpu_fecs_host_intr_status fecs_host_intr; u32 chid = isr_data->ch != NULL ? - isr_data->ch->chid : FIFO_INVAL_CHANNEL_ID; + isr_data->ch->chid : NVGPU_INVALID_CHANNEL_ID; u32 mailbox_id = NVGPU_GR_FALCON_FECS_CTXSW_MAILBOX6; gr_fecs_intr = g->ops.gr.falcon.fecs_host_intr_status(g, @@ -712,7 +712,7 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g) ch = nvgpu_gr_intr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid); isr_data.ch = ch; - chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID; + chid = ch != NULL ? ch->chid : NVGPU_INVALID_CHANNEL_ID; if (ch == NULL) { nvgpu_err(g, "pgraph intr: 0x%08x, chid: INVALID", gr_intr); @@ -788,7 +788,7 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g) * register using set_falcon[4] */ if (intr_info.fw_method != 0U) { u32 ch_id = isr_data.ch != NULL ? - isr_data.ch->chid : FIFO_INVAL_CHANNEL_ID; + isr_data.ch->chid : NVGPU_INVALID_CHANNEL_ID; nvgpu_err(g, "firmware method 0x%08x, offset 0x%08x for channel %u", isr_data.class_num, isr_data.offset, diff --git a/drivers/gpu/nvgpu/common/rc/rc.c b/drivers/gpu/nvgpu/common/rc/rc.c index d359ba0ae..5fd5e1008 100644 --- a/drivers/gpu/nvgpu/common/rc/rc.c +++ b/drivers/gpu/nvgpu/common/rc/rc.c @@ -138,7 +138,7 @@ void nvgpu_rc_gr_fault(struct gk20a *g, struct tsg_gk20a *tsg, u32 gr_eng_bitmask = 0U; gr_engine_id = nvgpu_engine_get_gr_id(g); - if (gr_engine_id != FIFO_INVAL_ENGINE_ID) { + if (gr_engine_id != NVGPU_INVALID_ENG_ID) { gr_eng_bitmask = BIT32(gr_engine_id); } else { nvgpu_warn(g, "gr_engine_id is invalid"); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 2d307dc61..31d9da519 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -31,17 +31,9 @@ #include #include -struct gk20a_debug_output; struct channel_gk20a; struct tsg_gk20a; -#define FIFO_INVAL_ENGINE_ID (~U32(0U)) -#define FIFO_INVAL_MMU_ID (~U32(0U)) -#define FIFO_INVAL_CHANNEL_ID (~U32(0U)) -#define FIFO_INVAL_TSG_ID (~U32(0U)) -#define FIFO_INVAL_RUNLIST_ID (~U32(0U)) -#define FIFO_INVAL_SYNCPT_ID (~U32(0U)) - struct fifo_gk20a { struct gk20a *g; unsigned int num_channels; diff --git a/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c index 76d6a9db5..d20a21c0a 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c @@ -366,7 +366,7 @@ void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g, u32 reg_val; u32 addr_lo, addr_hi; u64 inst_ptr; - u32 chid = FIFO_INVAL_CHANNEL_ID; + u32 chid = NVGPU_INVALID_CHANNEL_ID; struct channel_gk20a *refch; (void) memset(mmufault, 0, sizeof(*mmufault)); diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gk20a.c index c251babed..1ff24feb2 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gk20a.c @@ -88,7 +88,7 @@ bool gk20a_fifo_handle_ctxsw_timeout(struct gk20a *g) * context caused the problem as maybe more switches occurred before * intr is handled. */ - if (engine_id == FIFO_INVAL_ENGINE_ID) { + if (engine_id == NVGPU_INVALID_ENG_ID) { nvgpu_info(g, "fifo ctxsw timeout: 0x%08x, failed to find engine " "that is busy doing ctxsw. " "May be ctxsw already happened", sched_error); diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b.c index a29b7d8fd..a88aec1f2 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b.c @@ -90,7 +90,7 @@ void gv11b_fifo_ctxsw_timeout_enable(struct gk20a *g, bool enable) static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id, u32 *info_status) { - u32 tsgid = FIFO_INVAL_TSG_ID; + u32 tsgid = NVGPU_INVALID_TSG_ID; u32 timeout_info; u32 ctx_status; @@ -158,14 +158,14 @@ static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id, nvgpu_log_info(g, "ctxsw timeout info : ack received"); /* no need to recover */ - tsgid = FIFO_INVAL_TSG_ID; + tsgid = NVGPU_INVALID_TSG_ID; } else if (*info_status == fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v()) { nvgpu_log_info(g, "ctxsw timeout info : dropped timeout"); /* no need to recover */ - tsgid = FIFO_INVAL_TSG_ID; + tsgid = NVGPU_INVALID_TSG_ID; } return tsgid; @@ -174,7 +174,7 @@ static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id, bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g) { bool recover = false; - u32 tsgid = FIFO_INVAL_TSG_ID; + u32 tsgid = NVGPU_INVALID_TSG_ID; u32 engine_id, active_eng_id; u32 timeout_val, ctxsw_timeout_engines; u32 info_status; diff --git a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c index 09ba3d818..db1790ec3 100644 --- a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c @@ -334,7 +334,7 @@ bool gk20a_fifo_handle_mmu_fault_locked( } /* check if engine reset should be deferred */ - if (engine_id != FIFO_INVAL_ENGINE_ID) { + if (engine_id != NVGPU_INVALID_ENG_ID) { bool defer = nvgpu_engine_should_defer_reset(g, engine_id, mmfault_info.client_type, fake_fault); diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c index 213dd82ce..725a27e9d 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c @@ -426,7 +426,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg) runlist_id = tsg->runlist_id; nvgpu_log_fn(g, "runlist_id: %d", runlist_id); - if (runlist_id == FIFO_INVAL_RUNLIST_ID) { + if (runlist_id == NVGPU_INVALID_RUNLIST_ID) { return 0; } diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c index cfa9bbc57..41aec557d 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -36,8 +37,6 @@ #include -#define NVGPU_GR_FIFO_INVAL_CHANNEL_ID (~U32(0U)) - static int gp10b_gr_intr_clear_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) { @@ -63,7 +62,7 @@ static int gp10b_gr_intr_clear_cilp_preempt_pending(struct gk20a *g, } nvgpu_gr_ctx_set_cilp_preempt_pending(gr_ctx, false); - g->gr->cilp_preempt_pending_chid = NVGPU_GR_FIFO_INVAL_CHANNEL_ID; + g->gr->cilp_preempt_pending_chid = NVGPU_INVALID_CHANNEL_ID; return 0; } @@ -78,7 +77,7 @@ static int gp10b_gr_intr_get_cilp_preempt_pending_chid(struct gk20a *g, int ret = -EINVAL; chid = g->gr->cilp_preempt_pending_chid; - if (chid == NVGPU_GR_FIFO_INVAL_CHANNEL_ID) { + if (chid == NVGPU_INVALID_CHANNEL_ID) { return ret; } @@ -110,7 +109,7 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g, struct nvgpu_gr_isr_data *isr_data) { struct channel_gk20a *ch; - u32 chid = FIFO_INVAL_CHANNEL_ID; + u32 chid = NVGPU_INVALID_CHANNEL_ID; int ret = 0; struct tsg_gk20a *tsg; struct nvgpu_fecs_host_intr_status fecs_host_intr; @@ -137,7 +136,7 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g, fecs_host_intr.ctxsw_intr1); ret = gp10b_gr_intr_get_cilp_preempt_pending_chid(g, &chid); - if ((ret != 0) || (chid == FIFO_INVAL_CHANNEL_ID)) { + if ((ret != 0) || (chid == NVGPU_INVALID_CHANNEL_ID)) { goto clean_up; } diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c index 441551545..bdb2f74dc 100644 --- a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c +++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c @@ -184,7 +184,7 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g, u32 rd32_val; u32 addr_lo, addr_hi; u64 inst_ptr; - u32 chid = FIFO_INVAL_CHANNEL_ID; + u32 chid = NVGPU_INVALID_CHANNEL_ID; struct channel_gk20a *refch; (void) memset(mmufault, 0, sizeof(*mmufault)); @@ -287,7 +287,7 @@ void gv11b_gmmu_handle_mmu_fault_common(struct gk20a *g, unsigned int id_type = ID_TYPE_UNKNOWN; u32 num_lce, act_eng_bitmask = 0U; int err = 0; - u32 id = FIFO_INVAL_TSG_ID; + u32 id = NVGPU_INVALID_TSG_ID; unsigned int rc_type = RC_TYPE_NO_RC; struct tsg_gk20a *tsg = NULL; @@ -379,7 +379,7 @@ void gv11b_gmmu_handle_mmu_fault_common(struct gk20a *g, } /* engine is faulted */ - if (mmufault->faulted_engine != FIFO_INVAL_ENGINE_ID) { + if (mmufault->faulted_engine != NVGPU_INVALID_ENG_ID) { act_eng_bitmask = BIT32(mmufault->faulted_engine); rc_type = RC_TYPE_MMU_FAULT; } diff --git a/drivers/gpu/nvgpu/hal/rc/rc_gk20a.c b/drivers/gpu/nvgpu/hal/rc/rc_gk20a.c index 6aaaf3e0f..913891e39 100644 --- a/drivers/gpu/nvgpu/hal/rc/rc_gk20a.c +++ b/drivers/gpu/nvgpu/hal/rc/rc_gk20a.c @@ -76,7 +76,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 eng_bitmask, u32 mmu_id = nvgpu_engine_id_to_mmu_fault_id(g, (u32)engine_id); - if (mmu_id != FIFO_INVAL_ENGINE_ID) { + if (mmu_id != NVGPU_INVALID_ENG_ID) { mmu_fault_engines |= BIT(mmu_id); } } @@ -106,7 +106,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 eng_bitmask, active_engine_id); engine_ids |= BIT(active_engine_id); - if (mmu_id != FIFO_INVAL_ENGINE_ID) { + if (mmu_id != NVGPU_INVALID_ENG_ID) { mmu_fault_engines |= BIT(mmu_id); } } diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index a61ce9139..65d5d4688 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -32,6 +32,8 @@ #include #include +#define NVGPU_INVALID_CHANNEL_ID (~U32(0U)) + struct gk20a; struct dbg_session_gk20a; struct nvgpu_fence_type; diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h index eaa7fb6f3..894e50efb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h @@ -30,6 +30,8 @@ #include #include +#define NVGPU_INVALID_SYNCPT_ID (~U32(0U)) + struct channel_gk20a; struct nvgpu_channel_sync_syncpt; @@ -72,7 +74,7 @@ nvgpu_channel_sync_syncpt_create(struct channel_gk20a *c, static inline u32 nvgpu_channel_sync_get_syncpt_id( struct nvgpu_channel_sync_syncpt *s) { - return FIFO_INVAL_SYNCPT_ID; + return NVGPU_INVALID_SYNCPT_ID; } static inline u64 nvgpu_channel_sync_get_syncpt_address( struct nvgpu_channel_sync_syncpt *s) diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index 250181a26..9b4e471da 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -25,6 +25,8 @@ #include +#define NVGPU_INVALID_ENG_ID (~U32(0U)) + struct gk20a; struct fifo_gk20a; diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h index f5d862c2b..b398b8df5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h @@ -45,6 +45,8 @@ struct channel_gk20a; #define MAX_RUNLIST_BUFFERS 2U +#define NVGPU_INVALID_RUNLIST_ID (~U32(0U)) + struct nvgpu_runlist_info { u32 runlist_id; unsigned long *active_channels; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 47602d541..ab229298c 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "common/gr/gr_priv.h" @@ -457,7 +458,7 @@ static int gk20a_ctrl_prepare_compressible_read( args->fence.syncpt_value = fence_out->syncpt_value; } else { - args->fence.syncpt_id = FIFO_INVAL_SYNCPT_ID; + args->fence.syncpt_id = NVGPU_INVALID_SYNCPT_ID; args->fence.syncpt_value = 0; } }