From 398a30a546e0b9be5b3dd450b6ce7d90d379057d Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Tue, 6 Dec 2022 09:13:43 +0000 Subject: [PATCH] gpu: nvgpu: gsp sched: get the binary file names as per debug fuse Changes 1. Created gsp hal function to read the hardware config register to tell whether the board is debug fused. 2. Created function to get the binary file names as per debug fuse. NVGPU-9295 Bug 3897331 Signed-off-by: rmylavarapu Change-Id: Ia8462aa6f3d8d0d538c06f35245c965e106b3d37 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822443 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Mahantesh Kumbar GVS: Gerrit_Virtual_Submit --- .../gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c | 14 +++++++++----- .../gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.h | 10 +++++++--- drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c | 14 ++++++++++++++ drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h | 1 + drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gsp.h | 6 +++--- .../nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h | 3 +++ 8 files changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c index 3977029d0..2d39e8004 100644 --- a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c +++ b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c @@ -35,11 +35,15 @@ static void gsp_sched_get_file_names(struct gk20a *g, struct gsp_fw *gsp_ucode) { - nvgpu_gsp_dbg(g, " "); - - gsp_ucode->code_name = GSP_DBG_RISCV_FW_CODE; - gsp_ucode->data_name = GSP_DBG_RISCV_FW_DATA; - gsp_ucode->manifest_name = GSP_DBG_RISCV_FW_MANIFEST; + if (!g->ops.gsp.is_debug_mode_enabled(g)) { + gsp_ucode->code_name = SAFETY_SCHED_RISCV_FW_CODE_PROD; + gsp_ucode->data_name = SAFETY_SCHED_RISCV_FW_DATA_PROD; + gsp_ucode->manifest_name = SAFETY_SCHED_RISCV_FW_MANIFEST_PROD; + } else { + gsp_ucode->code_name = SAFETY_SCHED_RISCV_FW_CODE; + gsp_ucode->data_name = SAFETY_SCHED_RISCV_FW_DATA; + gsp_ucode->manifest_name = SAFETY_SCHED_RISCV_FW_MANIFEST; + } } void nvgpu_gsp_sched_suspend(struct gk20a *g, struct nvgpu_gsp_sched *gsp_sched) diff --git a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.h b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.h index 4a68df11e..5f7fc9ffe 100644 --- a/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.h +++ b/drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.h @@ -28,9 +28,13 @@ #define GSP_QUEUE_NUM 2U -#define GSP_DBG_RISCV_FW_MANIFEST "sample-gsp.manifest.encrypt.bin.out.bin" -#define GSP_DBG_RISCV_FW_CODE "sample-gsp.text.encrypt.bin" -#define GSP_DBG_RISCV_FW_DATA "sample-gsp.data.encrypt.bin" +#define SAFETY_SCHED_RISCV_FW_MANIFEST "safety-scheduler.manifest.encrypt.bin.out.bin" +#define SAFETY_SCHED_RISCV_FW_CODE "safety-scheduler.text.encrypt.bin" +#define SAFETY_SCHED_RISCV_FW_DATA "safety-scheduler.data.encrypt.bin" + +#define SAFETY_SCHED_RISCV_FW_MANIFEST_PROD "safety-scheduler.manifest.encrypt.bin.out.bin.prod" +#define SAFETY_SCHED_RISCV_FW_CODE_PROD "safety-scheduler.text.encrypt.bin.prod" +#define SAFETY_SCHED_RISCV_FW_DATA_PROD "safety-scheduler.data.encrypt.bin.prod" /* GSP descriptor's */ struct nvgpu_gsp_sched { diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c index 48d614aaf..e27542e33 100644 --- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c @@ -121,6 +121,20 @@ bool ga10b_gsp_validate_mem_integrity(struct gk20a *g) false); } +bool ga10b_gsp_is_debug_mode_en(struct gk20a *g) +{ + u32 ctl_stat = nvgpu_readl(g, pgsp_falcon_hwcfg2_r()); + + if (pgsp_falcon_hwcfg2_dbgmode_v(ctl_stat) == + pgsp_falcon_hwcfg2_dbgmode_enable_v()) { + nvgpu_info(g, "DEBUG MODE"); + return true; + } else { + nvgpu_info(g, "PROD MODE"); + return false; + } +} + #ifdef CONFIG_NVGPU_GSP_SCHEDULER u32 ga10b_gsp_queue_head_r(u32 i) { diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h index 5396e9708..047e540ba 100644 --- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h +++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h @@ -27,6 +27,7 @@ u32 ga10b_gsp_falcon_base_addr(void); u32 ga10b_gsp_falcon2_base_addr(void); int ga10b_gsp_engine_reset(struct gk20a *g); bool ga10b_gsp_validate_mem_integrity(struct gk20a *g); +bool ga10b_gsp_is_debug_mode_en(struct gk20a *g); #ifdef CONFIG_NVGPU_GSP_SCHEDULER void ga10b_gsp_flcn_setup_boot_config(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 92c5417dd..5ae8b42b8 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1318,6 +1318,7 @@ static const struct gops_gsp ga10b_ops_gsp = { .falcon2_base_addr = ga10b_gsp_falcon2_base_addr, .gsp_reset = ga10b_gsp_engine_reset, .validate_mem_integrity = ga10b_gsp_validate_mem_integrity, + .is_debug_mode_enabled = ga10b_gsp_is_debug_mode_en, #ifdef CONFIG_NVGPU_GSP_SCHEDULER /* interrupt */ .enable_irq = ga10b_gsp_enable_irq, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h index 0a16f18de..b513208bf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h @@ -35,6 +35,7 @@ struct gops_gsp { void (*falcon_setup_boot_config)(struct gk20a *g); int (*gsp_reset)(struct gk20a *g); bool (*validate_mem_integrity)(struct gk20a *g); + bool (*is_debug_mode_enabled)(struct gk20a *g); #ifdef CONFIG_NVGPU_GSP_SCHEDULER u32 (*gsp_get_queue_head)(u32 i); u32 (*gsp_get_queue_head_size)(void); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gsp.h b/drivers/gpu/nvgpu/include/nvgpu/gsp.h index e8ccb2e67..8dca3406b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gsp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gsp.h @@ -34,9 +34,9 @@ struct nvgpu_runlist; struct gsp_fw { /* gsp ucode name */ - char *code_name; - char *data_name; - char *manifest_name; + const char *code_name; + const char *data_name; + const char *manifest_name; /* gsp ucode */ struct nvgpu_firmware *code; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h index 6e3e769e1..46f789194 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h @@ -120,6 +120,9 @@ #define pgsp_falcon_hwcfg1_dmem_tag_width_f(v) ((U32(v) & 0x1fU) << 21U) #define pgsp_falcon_hwcfg1_dmem_tag_width_m() (U32(0x1fU) << 21U) #define pgsp_falcon_hwcfg1_dmem_tag_width_v(r) (((r) >> 21U) & 0x1fU) +#define pgsp_falcon_hwcfg2_r() (0x001100f4U) +#define pgsp_falcon_hwcfg2_dbgmode_v(r) (((r) >> 3U) & 0x1U) +#define pgsp_falcon_hwcfg2_dbgmode_enable_v() (0x00000001U) #define pgsp_ememc_r(i)\ (nvgpu_safe_add_u32(0x00110ac0U, nvgpu_safe_mult_u32((i), 8U))) #define pgsp_ememc__size_1_v() (0x00000004U)