diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index b48148abd..69d63590e 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -550,7 +550,9 @@ gr: hal/gr/falcon/gr_falcon_gv11b.h ] falcon: safe: no - sources: [ hal/gr/falcon/gr_falcon_gm20b.c ] + sources: [ hal/gr/falcon/gr_falcon_gm20b.c, + hal/gr/falcon/gr_falcon_tu104.c, + hal/gr/falcon/gr_falcon_tu104.h ] fecs_trace: safe: no sources: [ hal/gr/fecs_trace/fecs_trace_gm20b.c, diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 922cfe889..036237992 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -107,6 +107,7 @@ nvgpu-$(CONFIG_NVGPU_DGPU) += \ hal/gr/init/gr_init_gv100.o \ hal/gr/init/gr_init_tu104.o \ hal/gr/intr/gr_intr_tu104.o \ + hal/gr/falcon/gr_falcon_tu104.o \ hal/fbpa/fbpa_tu104.o \ hal/init/hal_tu104.o \ hal/init/hal_tu104_litter.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index c631e41f2..ba3c1aef8 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -626,6 +626,7 @@ srcs += common/sec2/sec2.c \ hal/gr/init/gr_init_gv100.c \ hal/gr/init/gr_init_tu104.c \ hal/gr/intr/gr_intr_tu104.c \ + hal/gr/falcon/gr_falcon_tu104.c \ hal/fbpa/fbpa_tu104.c \ hal/init/hal_tu104.c \ hal/init/hal_tu104_litter.c \ diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.c new file mode 100644 index 000000000..0e598a7db --- /dev/null +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gr_falcon_gm20b.h" +#include "gr_falcon_gv11b.h" +#include "gr_falcon_tu104.h" +#include "common/gr/gr_falcon_priv.h" + +#include + +int tu104_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, + u32 data, u32 *ret_val) +{ +#if defined(CONFIG_NVGPU_DEBUGGER) || defined(CONFIG_NVGPU_PROFILER) + struct nvgpu_fecs_method_op op = { + .mailbox = { .id = 0U, .data = 0U, .ret = NULL, + .clr = ~U32(0U), .ok = 0U, .fail = 0U}, + .method.data = 0U, + .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP, + }; + u32 flags = 0U; +#endif + int ret; + + nvgpu_log_info(g, "fecs method %d data 0x%x ret_val %p", + fecs_method, data, ret_val); + + switch (fecs_method) { +#if defined(CONFIG_NVGPU_DEBUGGER) || defined(CONFIG_NVGPU_PROFILER) + case NVGPU_GR_FALCON_METHOD_START_SMPC_GLOBAL_MODE: + op.method.addr = + gr_fecs_method_push_adr_smpc_global_mode_start_v(); + op.method.data = ~U32(0U); + op.mailbox.id = 1U; + op.mailbox.ok = gr_fecs_ctxsw_mailbox_value_pass_v(); + op.mailbox.fail = gr_fecs_ctxsw_mailbox_value_fail_v(); + op.cond.ok = GR_IS_UCODE_OP_EQUAL; + op.cond.fail = GR_IS_UCODE_OP_EQUAL; + flags |= NVGPU_GR_FALCON_SUBMIT_METHOD_F_SLEEP; + + ret = gm20b_gr_falcon_submit_fecs_method_op(g, op, flags); + break; + + case NVGPU_GR_FALCON_METHOD_STOP_SMPC_GLOBAL_MODE: + op.method.addr = + gr_fecs_method_push_adr_smpc_global_mode_stop_v(); + op.method.data = ~U32(0U); + op.mailbox.id = 1U; + op.mailbox.ok = gr_fecs_ctxsw_mailbox_value_pass_v(); + op.mailbox.fail = gr_fecs_ctxsw_mailbox_value_fail_v(); + op.cond.ok = GR_IS_UCODE_OP_EQUAL; + op.cond.fail = GR_IS_UCODE_OP_EQUAL; + flags |= NVGPU_GR_FALCON_SUBMIT_METHOD_F_SLEEP; + + ret = gm20b_gr_falcon_submit_fecs_method_op(g, op, flags); + break; +#endif + + default: + ret = gv11b_gr_falcon_ctrl_ctxsw(g, fecs_method, + data, ret_val); + break; + } + return ret; +} diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.h b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.h new file mode 100644 index 000000000..de9d73997 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_tu104.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GR_FALCON_TU104_H +#define NVGPU_GR_FALCON_TU104_H + +#include + +struct gk20a; + +int tu104_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, + u32 data, u32 *ret_val); + +#endif /* NVGPU_GR_FALCON_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c index 410fe3a2b..731d8aa7e 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gr_pri_gk20a.h" #include "gr_tu104.h" @@ -109,3 +110,20 @@ void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, *sm_dsm_perf_ctrl_regs = NULL; *ctrl_register_stride = 0; } + +int tu104_gr_update_smpc_global_mode(struct gk20a *g, bool enable) +{ + int err; + + if (enable) { + err = g->ops.gr.falcon.ctrl_ctxsw(g, + NVGPU_GR_FALCON_METHOD_START_SMPC_GLOBAL_MODE, + 0U, NULL); + } else { + err = g->ops.gr.falcon.ctrl_ctxsw(g, + NVGPU_GR_FALCON_METHOD_STOP_SMPC_GLOBAL_MODE, + 0U, NULL); + } + + return err; +} diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h index e10522935..f029e4da3 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h @@ -39,5 +39,6 @@ void gr_tu104_init_sm_dsm_reg_info(void); void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, u32 *num_sm_dsm_perf_ctrl_regs, u32 **sm_dsm_perf_ctrl_regs, u32 *ctrl_register_stride); +int tu104_gr_update_smpc_global_mode(struct gk20a *g, bool enable); #endif /* CONFIG_NVGPU_DEBUGGER */ #endif /* NVGPU_GR_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 37b0d7006..7b7503e0f 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -123,6 +123,7 @@ #include "hal/gr/falcon/gr_falcon_gm20b.h" #include "hal/gr/falcon/gr_falcon_gp10b.h" #include "hal/gr/falcon/gr_falcon_gv11b.h" +#include "hal/gr/falcon/gr_falcon_tu104.h" #include "hal/gr/config/gr_config_gm20b.h" #include "hal/gr/config/gr_config_gv100.h" #ifdef CONFIG_NVGPU_GRAPHICS @@ -366,6 +367,7 @@ static const struct gpu_ops tu104_ops = { .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .bpt_reg_info = gv11b_gr_bpt_reg_info, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, + .update_smpc_global_mode = tu104_gr_update_smpc_global_mode, .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, .set_pmm_register = gr_gv100_set_pmm_register, .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, @@ -805,7 +807,7 @@ static const struct gpu_ops tu104_ops = { .wait_mem_scrubbing = gm20b_gr_falcon_wait_mem_scrubbing, .wait_ctxsw_ready = gm20b_gr_falcon_wait_ctxsw_ready, - .ctrl_ctxsw = gp10b_gr_falcon_ctrl_ctxsw, + .ctrl_ctxsw = tu104_gr_falcon_ctrl_ctxsw, .get_current_ctx = gm20b_gr_falcon_get_current_ctx, .get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr, .get_fecs_current_ctx_data = diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h index e173276b5..3395cd5d9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h @@ -1103,6 +1103,8 @@ struct gops_gr { int (*update_smpc_ctxsw_mode)(struct gk20a *g, struct nvgpu_tsg *tsg, bool enable); + int (*update_smpc_global_mode)(struct gk20a *g, + bool enable); int (*update_hwpm_ctxsw_mode)(struct gk20a *g, struct nvgpu_tsg *tsg, u64 gpu_va, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h index 8838c4ccc..0e2e92288 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h @@ -76,6 +76,11 @@ defined(CONFIG_NVGPU_CTXSW_FW_ERROR_CODE_TESTING) /** Falcon method to set watchdog timeout. */ #define NVGPU_GR_FALCON_METHOD_SET_WATCHDOG_TIMEOUT 14 +#if defined(CONFIG_NVGPU_DEBUGGER) || defined(CONFIG_NVGPU_PROFILER) +#define NVGPU_GR_FALCON_METHOD_START_SMPC_GLOBAL_MODE 15 +#define NVGPU_GR_FALCON_METHOD_STOP_SMPC_GLOBAL_MODE 16 +#endif + /** Sleep while waiting for Falcon ACK */ #define NVGPU_GR_FALCON_SUBMIT_METHOD_F_SLEEP BIT32(0) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h index 123ba03d3..a6e02e28d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h @@ -485,6 +485,8 @@ #define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) #define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ (0x0000003aU) +#define gr_fecs_method_push_adr_smpc_global_mode_start_v() (0x00000069U) +#define gr_fecs_method_push_adr_smpc_global_mode_stop_v() (0x0000006aU) #define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\ diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 00839a299..764fd8945 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -950,6 +950,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, struct gk20a *g = dbg_s->g; struct nvgpu_channel *ch_gk20a; struct nvgpu_tsg *tsg; + bool global_mode = false; nvgpu_log_fn(g, "%s smpc ctxsw mode = %d", g->name, args->mode); @@ -965,24 +966,36 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, ch_gk20a = nvgpu_dbg_gpu_get_session_channel(dbg_s); if (!ch_gk20a) { - nvgpu_err(g, - "no bound channel for smpc ctxsw mode update"); - err = -EINVAL; - goto clean_up; + global_mode = true; } - tsg = nvgpu_tsg_from_ch(ch_gk20a); - if (tsg == NULL) { - nvgpu_err(g, "channel not bound to TSG"); - err = -EINVAL; - goto clean_up; - } + if (global_mode) { + if (g->ops.gr.update_smpc_global_mode == NULL) { + nvgpu_err(g, "SMPC global mode not supported"); + err = -EINVAL; + goto clean_up; + } - err = g->ops.gr.update_smpc_ctxsw_mode(g, tsg, + err = g->ops.gr.update_smpc_global_mode(g, args->mode == NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); - if (err) { - nvgpu_err(g, - "error (%d) during smpc ctxsw mode update", err); + if (err) { + nvgpu_err(g, + "error (%d) during smpc global mode update", err); + } + } else { + tsg = nvgpu_tsg_from_ch(ch_gk20a); + if (tsg == NULL) { + nvgpu_err(g, "channel not bound to TSG"); + err = -EINVAL; + goto clean_up; + } + + err = g->ops.gr.update_smpc_ctxsw_mode(g, tsg, + args->mode == NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); + if (err) { + nvgpu_err(g, + "error (%d) during smpc ctxsw mode update", err); + } } clean_up: