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gpu: nvgpu: vgpu: T18x support

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Add vgpu framework and build for T18x.

Bug 1677153
JIRA VFND-693

Change-Id: Icf9fd8e0b5769228aee59c54f9b000b992e5fcca
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/792559
Reviewed-on: http://git-master/r/806178
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Aingara Paramakuru
2015-08-27 13:53:47 -04:00
committed by Terje Bergstrom
parent ce4dd7ef86
commit 39e8bff2fc
4 changed files with 29 additions and 5 deletions
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7
drivers/gpu/nvgpu/vgpu/gr_vgpu.c
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@@ -99,7 +99,7 @@ static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g)
u32 cb_buffer_size = gr->bundle_cb_default_size *
gr_scc_bundle_cb_size_div_256b_byte_granularity_v();
u32 pagepool_buffer_size = gr_scc_pagepool_total_pages_hwmax_value_v() *
u32 pagepool_buffer_size = g->ops.gr.pagepool_default_size(g) *
gr_scc_pagepool_total_pages_byte_granularity_v();
gk20a_dbg_fn("");
@@ -530,6 +530,11 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
&gr->max_tpc_count))
return -ENOMEM;
if (vgpu_get_attribute(platform->virt_handle,
TEGRA_VGPU_ATTRIB_TPC_COUNT,
&gr->tpc_count))
return -ENOMEM;
gr->gpc_tpc_mask = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
if (!gr->gpc_tpc_mask) {
gk20a_err(dev_from_gk20a(g), "%s: out of memory\n", __func__);

14
drivers/gpu/nvgpu/vgpu/mm_vgpu.c
View File

@@ -53,9 +53,18 @@ static int vgpu_init_mm_setup_sw(struct gk20a *g)
int vgpu_init_mm_support(struct gk20a *g)
{
int err;
gk20a_dbg_fn("");
return vgpu_init_mm_setup_sw(g);
err = vgpu_init_mm_setup_sw(g);
if (err)
return err;
if (g->ops.mm.init_mm_setup_hw)
err = g->ops.mm.init_mm_setup_hw(g);
return err;
}
static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
@@ -275,7 +284,7 @@ static int vgpu_vm_alloc_share(struct gk20a_as_share *as_share,
for (i = 0; i < gmmu_nr_page_sizes; i++)
vm->gmmu_page_sizes[i] = gmmu_page_sizes[i];
vm->big_pages = true;
vm->big_pages = !mm->disable_bigpage;
vm->big_page_size = big_page_size;
vm->va_start = big_page_size << 10; /* create a one pde hole */
@@ -450,4 +459,5 @@ void vgpu_init_mm_ops(struct gpu_ops *gops)
gops->mm.tlb_invalidate = vgpu_mm_tlb_invalidate;
gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
gops->mm.get_iova_addr = gk20a_mm_iova_addr;
gops->mm.init_mm_setup_hw = NULL;
}

10
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -21,9 +21,12 @@
#include "gk20a/debug_gk20a.h"
#include "gk20a/hal_gk20a.h"
#include "gk20a/hw_mc_gk20a.h"
#include "gm20b/hal_gm20b.h"
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
#include "nvgpu_gpuid_t18x.h"
#endif
static inline int vgpu_comm_init(struct platform_device *pdev)
{
size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
@@ -270,6 +273,11 @@ static int vgpu_init_hal(struct gk20a *g)
gk20a_dbg_info("gm20b detected");
err = vgpu_gm20b_init_hal(g);
break;
#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
case TEGRA_18x_GPUID:
err = TEGRA_18x_GPUID_VGPU_HAL(g);
break;
#endif
default:
gk20a_err(&g->dev->dev, "no support for %x", ver);
err = -ENODEV;

3
include/linux/tegra_vgpu.h
View File

@@ -96,7 +96,8 @@ enum {
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE,
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE,
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC,
TEGRA_VGPU_ATTRIB_LTC_COUNT
TEGRA_VGPU_ATTRIB_LTC_COUNT,
TEGRA_VGPU_ATTRIB_TPC_COUNT
};
struct tegra_vgpu_attrib_params {