From 39eef614163713e81496362371d30c4620a0d235 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 12 Jul 2019 15:21:51 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA violation common.gr.gr Rule 10.6 forbids assignment of an 32-bit expression to a 64-bit target. This patch fixes MISRA 10.6 violations in common/gr/gr.c. Jira NVGPU-3808 Change-Id: I2fbe4a6fc7550acda1a8dbf545e35eff1e1fde39 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2152629 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index aa2094967..1291c973a 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -320,11 +320,11 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr) map_shift = map_bit & 0x7U; /* i.e. 0-7 */ nvgpu_log_info(g, "access map addr:0x%x byte:0x%x bit:%d", whitelist[w], map_byte, map_shift); - x = nvgpu_mem_rd32(g, mem, map_byte / (u32)sizeof(u32)); + x = nvgpu_mem_rd32(g, mem, (u64)map_byte / (u64)sizeof(u32)); x |= BIT32( (map_byte % (u32)sizeof(u32) * BITS_PER_BYTE_U32) + map_shift); - nvgpu_mem_wr32(g, mem, map_byte / (u32)sizeof(u32), x); + nvgpu_mem_wr32(g, mem, (u64)map_byte / (u64)sizeof(u32), x); } return 0;