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Revert "gpu: nvgpu: modify nvgpu_writel check and loop"

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This reverts commit c100ac23455d450a7046c62915014111a0aa2e70.

Bug 3009270

Change-Id: I1db1acac63c841b5383d75ec674fdc2160a0c84d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2356076
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
This commit is contained in:
Tejal Kudav
2020-06-04 23:29:27 -07:00
committed by Alex Waterman
parent 3156f32c08
commit 3a11bd69e7
5 changed files with 31 additions and 33 deletions
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17
drivers/gpu/nvgpu/common/io/io.c
View File

@@ -23,7 +23,6 @@
#include <nvgpu/io.h>
#include <nvgpu/types.h>
#include <nvgpu/bug.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/gk20a.h>
void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v)
@@ -35,20 +34,6 @@ void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v)
if (v != read_val) {
nvgpu_err(g, "r=0x%x rd=0x%x wr=0x%x (mismatch)",
r, read_val, v);
nvgpu_assert(v == read_val);
BUG_ON(1);
}
}
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v, u32 retries)
{
u32 reg_val = 0U;
nvgpu_writel(g, r, v);
do {
retries = nvgpu_safe_sub_u32(retries, 1U);
reg_val = nvgpu_readl(g, r);
} while ((reg_val != v) && (retries > 0U));
nvgpu_assert(reg_val == v);
}

19
drivers/gpu/nvgpu/hal/gr/zbc/zbc_gp10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,8 +28,6 @@
#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
#define NVGPU_WRITEL_LOOP_ZBC_RETRIES 20U
u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
{
return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r();
@@ -48,23 +46,18 @@ int gp10b_gr_zbc_add_color(struct gk20a *g,
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_c_format_reg(g);
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
nvgpu_gr_zbc_get_entry_color_ds(color_val, 0),
NVGPU_WRITEL_LOOP_ZBC_RETRIES);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 0));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
nvgpu_gr_zbc_get_entry_color_ds(color_val, 1),
NVGPU_WRITEL_LOOP_ZBC_RETRIES);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 1));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
nvgpu_gr_zbc_get_entry_color_ds(color_val, 2),
NVGPU_WRITEL_LOOP_ZBC_RETRIES);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 2));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
nvgpu_gr_zbc_get_entry_color_ds(color_val, 3),
NVGPU_WRITEL_LOOP_ZBC_RETRIES);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 3));
zbc_c = nvgpu_readl(g, zbc_c_format_reg + (index & ~3U));
zbc_c &= ~(0x7fU << ((index % 4U) * 7U));
zbc_c |= nvgpu_gr_zbc_get_entry_format(color_val) <<
((index % 4U) * 7U);
nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3U), zbc_c,
NVGPU_WRITEL_LOOP_ZBC_RETRIES);
nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3U), zbc_c);
return 0;
}

5
drivers/gpu/nvgpu/include/nvgpu/io.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -118,14 +118,13 @@ void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
* @param g [in] GPU super structure.
* @param r [in] Register offset in GPU IO space.
* @param v [in] Value to write at the offset.
* @param retries [in] Number of retries before failing.
*
* This is a blocking call. It keeps on writing a 32-bit value to a GPU
* register and reads it back until read/write values are not match.
*
* @return None.
*/
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v, u32 retries);
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v);
/**
* @brief Write a value to an already mapped bar1 io-region.

18
drivers/gpu/nvgpu/os/linux/linux-io.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -75,6 +75,22 @@ u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
return v;
}
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (unlikely(!l->regs)) {
nvgpu_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
} else {
nvgpu_wmb();
do {
writel_relaxed(v, l->regs + r);
} while (readl(l->regs + r) != v);
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
}
}
void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);

5
drivers/gpu/nvgpu/os/posix/posix-io.c
View File

@@ -107,6 +107,11 @@ u32 nvgpu_readl(struct gk20a *g, u32 r)
return access.value;
}
void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
{
BUG();
}
u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
{
struct nvgpu_posix_io_callbacks *callbacks =