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gpu: nvgpu: fix MMU fault register mismatches
Fix the following MMU register mismatches by using the appropriate HALs when possible: - fb_mmu_fault_status_r - fb_mmu_debug_ctrl_r Jira NVGPU-9217 Change-Id: I3380ac449f20f2ce47b439303b9abd19010e6b26 Signed-off-by: Austin Tajiri <atajiri@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869899 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* GM20B GPC MMU
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*
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* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -90,7 +90,7 @@ void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
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void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
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{
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gm20b_fb_set_mmu_debug_mode(g, enable);
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g->ops.fb.set_mmu_debug_mode(g, enable);
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g->ops.gr.set_debug_mode(g, enable);
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}
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#endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -587,7 +587,7 @@ void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
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#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
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void gv11b_fb_handle_replayable_mmu_fault(struct gk20a *g)
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{
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u32 fault_status = nvgpu_readl(g, fb_mmu_fault_status_r());
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u32 fault_status = g->ops.fb.read_mmu_fault_status(g);
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if ((fault_status & fb_mmu_fault_status_replayable_m()) == 0U) {
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return;
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