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gpu: nvgpu: add support for t19x tsg/channel

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Required modifications to add t19x channel
specific info and handle t19x tsg requests.

Bug 1842197

Change-Id: I0f8bcce20edea8f2f9a01e5bf5a9e4181af54875
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1511144
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-06-29 16:01:17 -07:00
committed by mobile promotions
parent a3802a2ae9
commit 3afac13d66
4 changed files with 25 additions and 1 deletions
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7
drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
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@@ -30,6 +30,9 @@
#include "ioctl_tsg.h" #include "ioctl_tsg.h"
#include "ioctl_channel.h" #include "ioctl_channel.h"
#include "os_linux.h" #include "os_linux.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "tsg_t19x.h"
#endif
struct tsg_private { struct tsg_private {
struct gk20a *g; struct gk20a *g;
@@ -469,9 +472,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
} }
default: default:
#ifdef CONFIG_TEGRA_19x_GPU
err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf);
#else
nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
cmd); cmd);
err = -ENOTTY; err = -ENOTTY;
#endif
break; break;
} }

4
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -858,6 +858,10 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
ch->obj_class = 0; ch->obj_class = 0;
ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
ch->timeslice_us = g->timeslice_low_priority_us; ch->timeslice_us = g->timeslice_low_priority_us;
#ifdef CONFIG_TEGRA_19x_GPU
memset(&ch->t19x, 0, sizeof(struct channel_t19x));
#endif
/* The channel is *not* runnable at this point. It still needs to have /* The channel is *not* runnable at this point. It still needs to have
* an address space bound and allocate a gpfifo and grctx. */ * an address space bound and allocate a gpfifo and grctx. */

6
drivers/gpu/nvgpu/gk20a/channel_gk20a.h
View File

@@ -36,6 +36,9 @@ struct fifo_profile_gk20a;
#include "mm_gk20a.h" #include "mm_gk20a.h"
#include "gr_gk20a.h" #include "gr_gk20a.h"
#include "fence_gk20a.h" #include "fence_gk20a.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "channel_t19x.h"
#endif
struct notification { struct notification {
struct { struct {
@@ -276,6 +279,9 @@ struct channel_gk20a {
u32 runlist_id; u32 runlist_id;
bool is_privileged_channel; bool is_privileged_channel;
#ifdef CONFIG_TEGRA_19x_GPU
struct channel_t19x t19x;
#endif
}; };
static inline struct channel_gk20a * static inline struct channel_gk20a *

9
include/uapi/linux/nvgpu.h
View File

@@ -970,11 +970,18 @@ struct nvgpu_gpu_set_event_filter_args {
#define NVGPU_IOCTL_TSG_GET_TIMESLICE \ #define NVGPU_IOCTL_TSG_GET_TIMESLICE \
_IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args)
#ifdef CONFIG_TEGRA_19x_GPU
#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
NVGPU_TSG_IOCTL_MAX_ARG
#define NVGPU_TSG_IOCTL_LAST \
_IOC_NR(NVGPU_TSG_IOCTL_MAX)
#else
#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
sizeof(struct nvgpu_event_id_ctrl_args) sizeof(struct nvgpu_event_id_ctrl_args)
#define NVGPU_TSG_IOCTL_LAST \ #define NVGPU_TSG_IOCTL_LAST \
_IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE) _IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE)
#endif
/* /*
* /dev/nvhost-dbg-gpu device * /dev/nvhost-dbg-gpu device